铪基高k栅介质/钝化层/Ge堆栈结构设计、界面调控及其MOS器件性能研究

The introduction of the high-k gate dielectric will lead to the formation of the unstable interfacial layer between high k layer and the substrate, and reduction of the carrier mobility of channel material, which will degrade device performance. Focus on this problem, HfRO (R=Gd, Dy)/interface passivation layer/Ge gate stacks will be built in this study. The Al2O3 interface passivation layer will be introduced by using atomic layer deposition (ALD) technology. The precursor of Al2O3 with “self-cleaning” effect can improve the interfacial quality of interface between high-k layer and Ge substrate.The Ti capping layer between electrode and the gate dielectric layer will be introduced by using electron beam evaporation technology. The oxygen scanvenge effect of Ti can furtherly optimize the quality of the interface.Through experiments, the effect of the doping content of rare earth element R,the introduction of the Al2O3 passivation layer and Ti capping layer on the interfacial properties, thermal stability, band offset and the electrical properties of Ge-MOS will be studied systematically. Relation between interfacial reaction mechanism and electrical properties will be analyzed,the optimized fabricating parameters for preparation of gate stacks will be determined. This study of subject will provide theoretical and experimental basis for the development of ALD technology for preparation of a new type of high-k gate stacks films with thermodynamical stability and Fermi level unpinning. It will provide the important scientific significance and practical value for the development of Ge-MOS.

高k栅介质的引入导致高k/Ge间不稳定界面层的生成和沟道载流子迁移率的退化，严重影响了Ge基MOS器件性能的提升。针对此关键问题，本项目提出构筑HfRO(R=Gd，Dy)/钝化层/Ge结构，采用原子层沉积（ALD）技术引入Al2O3钝化层，利用Al2O3前驱体对Ge的“自清洁”效应改善高k层与Ge衬底间界面质量；采用电子束蒸发技术在电极和栅介质间引入Ti盖帽层，利用Ti金属的“氧清除”效应进一步优化界面质量。通过研究稀土元素R掺杂量及Al2O3钝化层和Ti盖帽层的引入对Ge上HfRO/Al2O3叠层栅薄膜界面特性、热稳定性、能带偏移及Ge-MOS电学性能的影响，分析界面作用机制与电学性能的内在联系，确定栅介质薄膜最佳制备工艺参数。本课题的研究，将为发展ALD技术在Ge上实现热力学稳定、无费米能级钉扎的新型高k叠层栅提供理论和实验依据，对Ge-MOS的发展提供重要的理论及实验支持。

随着器件特征尺寸的缩小，沟道电场及其引发的散射不断增强，导致沟道载流子迁移率不断退化，器件性能受到严重影响，以应变硅为沟道的CMOS技术在速度和功耗方面将很难满足要求。本项目以获得实现高性能低功耗新型沟道材料MOS器件为导向，采用原子层沉积技术引入钝化层，利用原子层沉积金属前驱体的“自清洁”效应改善了高k层与衬底间界面质量。研究了稀土元素R掺杂及Al2O3钝化层的引入对HfRO/Al2O3叠层栅薄膜界面特性、热稳定性、能带偏移及MOS电学性能的影响，分析了界面作用机制与电学性能的内在联系，确定栅介质薄膜最佳制备工艺参数。项目执行期间，项目组成员系统开展了以下工作：（1）研究不同高k栅介质的制备、界面调控及MOS器件性能优化；（2）通过原子层沉积技术引入钝化层，成功实现了热力学稳定且无费米能级钉扎的新型高k栅介质/IPL/半导体叠层结构；（3）发展了高载流子迁移率沟道材料上稀土元素掺杂的Hf基薄膜制备技术，找出了满足未来栅介质材料要求的叠层材料。本课题的研究，为高性能新型MOSFET应用提供了理论和实验依据，有重要的科学意义和实用价值。在本项目的资助下，共发表17篇SCI论文，其中第一作者和通讯作者论文8篇。参加国内学术会议2次，申请相关发明专利3项（实审阶段）。指导研究生4名，同时为5名青年教师发展提供支持。

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