氮化镓基高空穴迁移率晶体管材料与器件研究

The GaN based digital circuit has the characteristics of high temperature resistance and radiation resistance. Therefore, it is expected to be applied in the high temperature and space field. In order to realize the GaN based digital circuit, the CMOS technology, which is one of the basic units of the digital circuit, is essential. The GaN based CMOS need not only GaN Based n-type channel field-effect transistor, but also p-type channel field-effect transistor which can complementary to the n-type device, for forming digital logic. This project intends to research selective epitaxial n-type gate technology to avoid injury 2DHG channel, obtain the technology of n-type gate epitaxial on GaN based HHMT, the method of optimize the interface of regrowth, manufacture GaN based HHMT devices with n-type gate. During the research process, the project will face many scientific and technological problems. It is not only the problem of GaN based p channel field-effect transistor, but also the common key technologies of GaN based power electronics, RF microwave and optoelectronics reseaches. The research of this project will further promote the research of p GaN based materials and devices, and improve the integrity of the research on GaN based materials.

GaN基数字电路具有耐高温与抗辐射等特点，有望用于高温环境与航天领域中。为了实现GaN基数字电路，组成数字电路的基本单元之一的CMOS技术是必不可少的。而CMOS技术中，不仅需要GaN基n型沟道场效应管，同时还需要与n型沟道场效应管互补的p型沟道场效应管，从而形成数字逻辑。本项目拟通过研究可规避沟道损伤的2DHG材料上选区外延n型栅技术，掌握GaN基HHMT材料上良好形貌n型栅外延技术，实现具有n型栅极的GaN基HHMT器件。研究过程中，项目还将面临并解决许多科学与技术问题，不仅是GaN基p型沟道场效应管的问题，还是包括GaN基电力电子、射频微波、光电领域的共性关键技术问题。开展本项目研究，将进一步推动p型GaN基材料与器件的研究，提升GaN基材料研究的完整度。

氮化镓基数字电路具有耐高温与抗辐射等特点，有望用于高温环境与航天领域中。为了实现GaN基数字电路，组成数字电路的基本单元之一的CMOS技术是必不可少的。而CMOS技术中，不仅需要GaN基n型沟道场效应管，同时还需要与n型沟道场效应管互补的p型沟道场效应管，从而形成数字逻辑。本项目利用选区外延生长技术，在HHMT外延材料上面的栅极位置选区生长一层n型GaN栅材料，从而耗尽栅下沟道的2DHG，实现GaN基增强型HHMT器件。此方法可以避免槽栅型增强器件工艺对沟道迁移率的限制，以及刻蚀n型栅极技术带来的2DHG损伤。研究中，首先通过调整载气、V/III比、源流量等，实现生长速率的稳定可控，成功实现了Si掺杂浓度超过2×10^20 cm^-3的再生长n+-GaN，载流子浓度约7.2×10^19 cm^-3，电子迁移率约150 cm^2/V·s，并明显降低材料表面Ⅴ坑密度，使表面粗糙度仅为1.087 nm@2×2 μm^2。其次分析掩膜种类、厚度以及制备工艺对二次外延界面的影响，探索选区生长窗口的表面处理工艺，减少表面态，获得较好的二次外延界面质量，获得正向开启压大于2V，反向漏电流小于1nA@-20V的PN结。

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