面向非易失存储的四方相铁酸铋与硅外延集成

Owing to its high speed, low power consumption, and excellent integration with silicon processing technologies, ferroelectric field-effect transistor (FeFET) based on the metal-ferroelectric-insulator-semiconductor stacks is one of most promising new-generation non-volatile memories. However, the ferroelectric layer in a typical FeFET has a thickness as high as several hundred nanometers, making it impossible for FeFET to be scalable down to the nanoscale. The rather low storage density is one of bottlenecks for the application of FeFET. Here we focus on this issue and try to find out ways to epitaxially integrate tetragonal BiFeO3 with silicon, by using a Bi2SiO5 buffer layer. Tetragonal BiFeO3 has the merits of low dielectric constant and high coercive field - the low dielectric constant insures a considerably large voltage drop across the ferroelectric layer, while the high coercive field favors a sufficient memory window, when reducing the ferroelectric thickness. Moreover, the interfacial chemical stability and the low lattice misfit of Bi2SiO5/silicon, as well as tetragonal BiFeO3/Bi2SiO5, make it feasible to obtain high-quality epitaxial films and thereby to reduce the leakage current. This project enables us to disclose the dynamic growth process of tetragonal BiFeO3 epilayer, to make clear the polarization symmetry, and to elucidate the tetragonal-to-rhombohedral structural relaxation process. It also gives us the chances to reduce the leakage current and enhance the storage density, and therefore offers a possibility to commercialize FeFET.

基于金属-铁电体-绝缘体-半导体结构的铁电场效应晶体管兼具高速、低能耗、与硅基工艺可完美集成的优点，有望应用于下一代非易失存储器。但铁电场效应晶体管中铁电层厚度通常高达数百纳米，使其很难等比缩小到纳米尺度。较低的存储密度成为制约铁电场效应晶体管发展的瓶颈之一。为解决这一问题，本项目拟借助Bi2SiO5（硅酸铋）缓冲层，实现四方相铁酸铋与硅的外延集成。四方相铁酸铋具有介电常数小、矫顽场大的优势。小的介电常数可确保在降低铁电层厚度的同时使其两端具有足够的分压，而大矫顽场则有利于保证器件的存储窗口。硅酸铋与硅及四方相铁酸铋间界面稳定性好、晶格失配度小，有助于获得高质量的外延薄膜并降低漏电。通过项目实施，期望揭示硅基四方相铁酸铋的外延生长动力学过程，澄清其极化对称性，阐明四方相到三方相的结构弛豫规律；同时探寻降低漏电、提高存储单元性能的可行途径，为高存储密度铁电场效应晶体管的实用化奠定坚实基础。

基于金属-铁电体-绝缘体-半导体结构(MFIS)的铁电场效应晶体管(FeFET)兼具高速、低能耗、与硅基工艺可完美集成的优点，有望应用于下一代非易失存储器。然而，铁电场效应晶体管中铁电层厚度通常高达数百纳米，使其很难等比缩小到纳米尺度。较低的存储密度成为制约铁电场效应晶体管发展的瓶颈之一。我们的研究显示，通过将具有小介电常数、大矫顽场的亚稳四方相BiFeO3与Si外延集成，可完美解决上述问题。要实现四方相 BiFeO3与 Si的外延集成，需要解决对称性失配、晶格失配及化学失配的难题。具有正交结构的 Bi2SiO5，在[100]取向时与 Si 和 BiFeO3的晶格失配度均很小，同时作为硅氧化物和铋氧化物又可解决化学失配的难题。以 Bi2SiO5作为缓冲层，我们成功实现了亚稳四方相 BiFeO3在 Si（001）衬底上的外延生长。我们发现，与常见的 MC极化对称性不同，BiFeO3表现出正四方对称性。在此基础上，我们制备了基于Au/四方 BiFeO3/Bi2SiO5/Si结构的MFIS 器件，存储窗口高达 6.5V，远大于此前文献报道的同等铁电层厚度情况下的数值。通过外推得到的四方 BiFeO3矫顽场为 240kV/cm，介电常数仅为16。我们的工作为高集成度、低能耗的FeFET研究开拓了可行的路径。而且，我们还研究了BiFeO3外延薄膜结构随应力及厚度的演变规律，阐明了BiFeO3外延薄膜在应力作用下的不同于传统认识的相变路径，丰富了对BiFeO3相图的认识。此外，我们还实现了四方相BiFeO3与ZnO的外延集成，为未来研制全氧化物FeFET奠定了基础。

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