面向集成电路IP硬核的多级协同混淆研究

Integrated circuit intellectual property (IP) core is a core component of the VLSI design. The IP core mainly includes soft core, firm core and hard core. Among the preformances of the three IP cores, the hard core is the most stable and reliable one. However, there are some vulnerabilities in hard core design and manufacturing process, which are prone to be attacked. Hardware obfuscation is one of the most effective methods for IP core protection. By the way of changing circuit peroperties and logic structure to concel its core functionality, it is degined to reduce the threat coming from Reverse Engineering, IP Piracy, Illegal Dissemination and Hardware Trojans. In view of this, aiming at protecting the hard IP core, the present project will place emphasis on the multilevel collaborative obfuscation techniques. Through extracting the different obfuscation parameters of the physical, circuit, logic and behavior levels, the internal relationship and transmission mechanism among different obfuscation levels can be revealed in the hard IP core. Based on this information, a safer hard IP core design will be developed. The research includes investigation of the mechanism and model construction of multilevel collaborative obfuscation, multilevel collaborative obfuscation of self-controllable firm IP core, system collaborative obfuscation of high performance hard IP core and the performance evaluation. The research results are expected to provide a foundamenal theory and methodology for IP core protection and to promote a better development of IC industry.

集成电路知识产权（Intellectual Property，IP）核是超大规模集成电路设计的核心部件，主要包括软核、固核和硬核，其中硬核性能最稳定可靠，但其自身在设计制造流程中也更容易遭受攻击。硬件混淆是诸多IP核保护中最有效的一种，通过改变电路属性或逻辑结构隐藏IP核功能，利用硬件特性保护内部重要信息，可以有效降低逆向工程、IP核盗用、非法传播及硬件木马等安全威胁。鉴此，项目将从IP固核入手，重点研究保护IP硬核安全的多级协同混淆技术。旨在通过对IP硬核的物理级、电路级、逻辑级和行为级混淆参数特征提取，揭示不同层次之间混淆的内在关系与传递机制，提出更安全的IP硬核设计方法。主要研究内容包括：多级协同混淆的机理和模型构建，自主可控IP固核的多级协同混淆，高性能IP硬核的系统协同混淆，多级协同混淆的性能评估等。研究成果将为IP核保护提供科学的理论依据和方法指导，推动集成电路产业的快速发展。

本项目通过对集成电路IP硬核的物理级、电路级、逻辑级和行为级混淆的研究，提取单层混淆参数特征和混淆因子，揭示不同层次之间混淆的内在关系与传递机制，构建多级协同混淆的数学模型；明确混淆因子的传递关系，建立多级联动混淆机制，解决IP硬核跨层次的系统协同混淆、混淆强度与混淆效率的平衡等问题，实现自主可控混淆IP固核和高性能、低成本混淆IP硬核。本项目课题组已顺利完成既定内容的研究，并针对集成电路安全性设计关键技术进行了拓展研究。本项目课题组已顺利完成既定内容的研究，并针对集成电路安全性设计关键技术进行了拓展研究。项目研究期间发表学术论文35篇，其中期刊论文29篇，国际学术会议论文6篇，SCI收录17篇，EI收录14篇；授权发明专利10项，其中授权美国发明专利3项。项目研究期间，1名教师由副教授晋升为教授，1名教师由讲师晋升为副教授；培养博士研究生2名，硕士研究生8名。研究成果将为IP核保护提供科学的理论依据和方法指导，推动集成电路产业的快速发展。

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