面向百核处理器Cache一致性协议的高效片上网络研究

The advancement of semiconduct technology continuously increases the core count. The industry has entered the era of hundred-core processors. The traditional bus communication mechanism has several disadvantages in hundred-core processors. The Network-on-Chip (NoC) effectively overcomes these disadvantages, and becomes the de facto communication standard for hundred-core processors. On the other hand, due to the difficulty of parallel programming and compatibility requirements of history codes, cache coherence protocols will exist in hundred-core platforms. However, coherence protocols in hundred-core processors face several challenges, including the increase of transaction latency, the hierachical structure, the growth of message count, and the bottleneck of multicast and reduction communication. To address these challenges, it is necessary to optimze the design of NoC based on the structure of the protocol and the characteristics of the coherent traffic. This project mainly researches on key techniques of designing efficient NoC to support the coherence protocols in hundred-core processors. We will delve into four research directions: 1. reconfigurable topology with low latency; 2. high performance routing algorithm which dynamically isolates different regions; 3. efficient flow control for short packets; 4. hardware support for multicast and reduction communication. The study of this project establishes a solid theoretical and technical foundation for the design of the communication mechanism for hundred-core processors. It has both important engineering value and theoretical significance.

半导体技术的发展不断增加芯片集成的核数，业界已进入百核处理器时代。片上网络较好地克服了传统总线互联结构的诸多不足，它已成为百核处理器事实上片内互联标准。另一方面，并行编程的高难度和兼容遗留代码的需求使得百核处理器依然采用cache 一致性协议，但百核处理器上的cache一致性协议面临着事务延迟上升、层次化结构、消息量剧增、多播和归约通信瓶颈诸多挑战。为缓解这些挑战，需要在分析一致性协议结构和通信特征的基础上优化设计片上网络。本课题主要研究高效支持百核处理器cache一致性协议的片上网络关键技术，包括低延迟的动态可重构拓扑结构、维持区域隔离的高性能路由算法、高效传输短报文的流控机制、多播和归约通信的硬件支持等。本课题的研究可以为百核处理器片内互联架构的设计与实现奠定坚实的理论和技术基础，具有重要的理论意义和应用价值。