纳米工艺下低功耗通信芯片关键模块的随机计算设计方法研究

The issue of unreliable signal transmission on chips is becoming more and more severe under nanoscale process, which hinders the communication chips from taking full advantage of the process advancement. Due to the statistical feature of performance evaluation for communication systems, stochastic computations could increase the reliability by introducing the circuit redundancy. However, such research is still far from completion. Currently, it is considerably hard to further decrease the power consumption of communication chips from the architecture, algorithm, and circuit levels. Based on the stochastic computations, this project utilizes the communication theory to analyze the reliable on-chip signal transmission under noisy and low voltage environment. It could decompose the conventional architecture of algorithm, architecture, and circuit for joint optimization. This project proposes the criterion and optimum method for decomposition for basic communication blocks, and the fusion algorithm for stochastic computations and sampling signal representations as well as the description method for distributed networks. It jointly designs the redundant circuit and architecture for memory under stochastic computations, which could be further applied to the critical blocks with high power consumption in communication chips, such as FFT and LDPC decoder. Thus, this project could lead to excellent solutions of low power consumption to even more complex communication chips. This research provides an important path to low power consumption communication systems, and enhances the understanding on the mechanism of stochastic computations in addition to nanoscale digital signal processing.

纳米工艺下片上信号的非可靠性传输问题日趋严重，使通信芯片不能充分利用半导体工艺进步的好处。由于通信系统性能评价的统计特性，随机计算能利用冗余电路提高其芯片实现的可靠性，但其研究尚处在起步阶段。目前单纯从架构，算法或电路上已很难进一步降低通信芯片的功耗。本课题基于随机计算，借鉴通信理论来研究在低电压下有噪片上信道中数据的可靠传输，突破通信关键模块的算法-架构-电路的框架进行联合优化，提出通信基本单元的可分解性判据和最优分解方法，提出随机网络计算与采样信号表示技术的融合算法以及在分布式网络上的描述方法，得到随机计算下存储器冗余电路和架构的联合设计，并将以上的方法应用于通信芯片中功耗较大的关键模块中，如FFT和LDPC译码器。进而为更复杂的通信芯片提供低功耗解决方案。开展随机计算下通信芯片关键模块设计的研究将为通信系统大幅降低功耗提供重要途径，并加深对随机计算和纳米级数字信号处理内在机理的理解。

本项目进展顺利，积极探索随机计算对于通信基带的影响，提出了一整套基于随机计算的降低功耗的算法和电路设计方法，并设计完成了两款基于随机计算的LDPC译码器，达到了吞吐率和功耗的良好的平衡，并完成了在65nmCMOS工艺下的芯片的10Gbase-T的流片验证，测试结果表明是目前基于随机计算的LDPC译码器的较好实现结果，单芯片吞吐率达到了62.53Gbps，功耗只有1.2W，比同等工艺条件下的同样码型，同样标准下的LDPC减少了14%,充分验证了提出的方法的有效性和可行性。以通信作者和第一作者发表论文8篇，其中发表在IEEE trans. on circuit and system II期刊两篇，在国际著名会议ASSCC，ISCAS，ICASSP等会议上宣口头报告6篇。申请发明专利15项，目前获得授权6项。培养博士硕士研究生6人。

内容获取失败，请点击重试