施主和受主掺杂SrTiO3单晶的阻变机制研究

The optical and Electrical properties of perovskite SrTiO3 is easily modulated through doping, so there are a wide range of potential applications in the preparation of the novel nonvolatile resistive switching memory. However, so far the resistive switching mechanism is not clear. Studied have shown that interfacial barrier and oxygen vacancied often exist in the SrTiO3 resistive devices, however, the donor doped SrTiO3 resistive change resulting from the interface barrier, and acceptor doped SrTiO3 resistance change is from conductive filament of oxygen vacancies. This has seriously hampered the further development and application. To solve the problem, this project intends to study SrTiO3 single crystal doped with different element, and a comprehensive analysis of the oxygen vacancies and interfacial barrier during resistance switching process. The main work carried out: (1)using magnetron sputtering and dual-chamber multiple evaporation coating deposited metal electrode on SrTiO3 single crystal, and constructing the metal electrode by a photolithography technique; (2)study the impact of interface and defects on resistive performance; (3) the combination of electrical, spectra and band theory calculations reveal the physical process and the microscopic mechanism. The implementation of this project for the development of high performance resistance-change memory to provide a theoretical basis and scientific guidance.

钙钛矿结构SrTiO3易通过元素掺杂调制其光电性能，在制备新型非易失性阻变存储器方面有潜在应用价值。然而至今其阻变机制尚不明确，研究表明界面势垒和氧空位常共同存在于SrTiO3阻变器件中，然而施主掺杂SrTiO3的阻变一般归因于界面势垒改变，而受主掺杂SrTiO3的阻变归因于氧空位导电细丝的形成和断裂。尚未明确的阻变机理严重制约了其研发和应用。针对该问题，本项目拟以不同元素掺杂的SrTiO3单晶为研究对象，综合分析"金属/SrTiO3"结构器件的阻变过程中氧空位和界面势垒所起作用。主要开展工作为：(1)采用磁控溅射和双室多元蒸发镀膜技术在SrTiO3单晶上沉积金属，并通过光刻技术构筑电极图形；(2)研究界面势垒、缺陷等对阻变性能的影响；(3)结合光电测试及理论分析，建立界面势垒、氧空位和阻变机制之间的有机联系和清晰完整的理论模型。本项目的实施将为研发高性能阻变存储器提供理论依据和科学指导。

本项目通过研究不同元素掺杂SrTiO3 (STO)的光电性能，揭示了Pt/STO结的界面势垒是影响阻变的关键因素。根据EPR和Raman结果，确定了掺杂STO单晶表面存在氧空位缺陷，其可作为电子俘获中心；同一种元素掺杂的STO，其缺陷的浓度随掺杂量的增大而增大。Pt/NdSTO/In器件的光电性能表明该器件具有多级存储，且光照下具有开路电压，阻态越高所对应的开路电压越大；这表明阻变由Pt/NdSTO界面势垒宽度和高度的变化引起，缺陷俘获去俘获电子是界面势垒改变的原因。Pt/NbSTO/In的研究结果表明0.7wt% NbSTO比0.05wt% NbSTO具有更稳定的阻态和大的开关比，证明调控界面缺陷浓度和内建电场可提高阻态稳定性和可区分度。对Pt/FeSTO/NbSTO/In器件，C-V结果表明存在带正电的界面缺陷态，缺陷态的充放电致使界面势垒改变，从而引起阻变存储；对比0.05wt%和0.7wt%NbSTO两种衬底所对应器件，前者具有更大的阻值，有效降低了器件功耗。.以上对多种元素掺杂STO的研究结果表明，Pt/STO结的阻变由界面势垒的改变所致，而界面势垒的改变是由界面缺陷俘获去俘获电子引起；调控内建电场和缺陷浓度可有效提高阻态稳定性、可区分度以及降低功耗等，从而有效改善存储性能。这些研究结果为研发高性能阻变存储器提供了直接理论依据和科学指导。

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