Computer-Aided Design for High-Performance Large-Scale Integrated Circuits

高性能大规模集成电路的计算机辅助设计

• 批准号: RGPIN-2020-04186
• 负责人: Najm, Farid
• 金额: $ 2.84万
• 依托单位: University of Toronto
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2022
• 资助国家: 加拿大
• 起止时间: 2022-01-01 至 2023-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=751632
• 关键词: Computer; Aided; Design; Performance; Large

With the deployment of electronics across the modern economy, there is a need to ensure the reliability of electronic devices and systems in a wide range of sectors. Integrated Circuits (ICs, or simply "chips") are subject to degradation and aging due to a number of failure mechanisms that can lead to chip failure, possibly months or years after deployment. We focus specifically on electromigration (EM) in metal lines, a failure mechanism that causes metal lines on a chip to degrade and fail under high current density. The impact of EM has gotten worse with the shrinking dimensions of modern IC technology. My group develops computer-aided design (CAD) tools to ensure chip robustness in the face of EM degradation. Traditional methods of EM checking are based on empirical models and involve checking the current densities in metal lines against specifications that are technology-specific, rather than design-specific. These methods are easy to use and have served the industry well, but have become inadequate for modern IC technology. Among other things, a key failing of these methods is that they cannot track the movement of metal atoms across metal branches, leading to much reduced accuracy. In our previous work, we have developed an efficient approach for physics-based (rather than empirical) EM checking, based on simulation of the mechanical stress that develops in metal lines under high current density. This allows us to track the movement of metal atoms across different branches in large multi-branch metal structures, providing significant accuracy improvement. We have thus developed the first-ever EM stress simulator [IRPS-19], which was recognized with a Best Paper Award in ICCAD-2016. However, stress simulation is more time-consuming than a simple current density check, so more work is required before these advances can be transferred to the industry. This project aims to address this need, with a key innovative approach for current constraints generation. This would involve formulating and solving the inverse of the stress simulation problem, and promises to deliver high-impact solutions to both the research community and the industry. In the simulation approach, a simulator takes in the given input current specifications and provides the mechanical stress over time. Instead, given a safety limit on the stress everywhere in a metal network, we propose to generate constraints on the branch currents which, if guaranteed by design, would ensure that the stress remains safe during the specified chip lifetime. One can then simply check during design if the branch current densities satisfy the generated current constraints. The overall approach would effectively translate the EM lifetime specification into a specification of branch current constraints that are both technology and design specific. It would combine the accuracy of stress-based analysis with the speed and simplicity of a current density check; it would be the best of both worlds.

随着电子产品在现代经济中的部署，需要确保各个领域的电子设备和系统的可靠性。集成电路（IC，或简称为“芯片”）由于多种可能导致芯片故障（可能在部署后数月或数年）的故障机制而容易退化和老化。我们特别关注金属线中的电迁移（EM），这是一种导致芯片上的金属线在高电流密度下退化和失效的故障机制。随着现代 IC 技术尺寸的缩小，EM 的影响变得更加严重。我的团队开发计算机辅助设计 (CAD) 工具，以确保芯片在电磁退化时的稳健性。传统的电磁检查方法基于经验模型，涉及根据特定技术而非特定设计的规范检查金属线中的电流密度。这些方法易于使用，并且很好地服务于整个行业，但对于现代 IC 技术来说已经不够了。除其他外，这些方法的一个主要缺点是它们无法跟踪金属原子跨金属分支的运动，导致准确性大大降低。在我们之前的工作中，我们基于对高电流密度下金属线中产生的机械应力的模拟，开发了一种基于物理（而不是经验）的电磁检查的有效方法。这使我们能够跟踪大型多分支金属结构中不同分支的金属原子的运动，从而显着提高准确性。因此，我们开发了有史以来第一个电磁应力模拟器 [IRPS-19]，并荣获 ICCAD-2016 最佳论文奖。然而，应力模拟比简单的电流密度检查更耗时，因此在将这些进步转移到行业之前还需要做更多的工作。该项目旨在通过针对当前约束生成的关键创新方法来满足这一需求。这将涉及制定和解决应力模拟问题的逆问题，并有望为研究界和行业提供高影响力的解决方案。在仿真方法中，模拟器接受给定的输入电流规格并提供随时间变化的机械应力。相反，考虑到金属网络中各处应力的安全限制，我们建议对分支电流产生约束，如果通过设计保证，将确保应力在指定的芯片寿命期间保持安全。然后，人们可以在设计期间简单地检查支路电流密度是否满足生成的电流约束。整体方法将有效地将 EM 寿命规范转化为技术和设计特定的支路电流约束规范。它将基于应力的分析的准确性与电流密度检查的速度和简单性结合起来；这将是两全其美的。