Hybrid approaches for functional verification of microelectronics systems

微电子系统功能验证的混合方法

• 批准号: 261438-2008
• 负责人: AitMohamed, Otmane
• 金额: $ 1.42万
• 依托单位: Concordia University
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2011
• 资助国家: 加拿大
• 起止时间: 2011-01-01 至 2012-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=479827
• 关键词: Hybrid; approaches; functional; verification; microelectronics

Today's digital circuits may contain up to several hundred million transistors. It is recognized that functional verification remains a major bottleneck of the design process, accouting for 70% of its overall costs. Functional verification by simulation is a way of finding bugs by deriving functional tests (testbench drivers) while attempting to reach functional coverage goals for the design. Finding corner-case bugs with simulation is often inefficient due to the limited controllability of the design through the testbench drivers. Writing a directed test to exercise a specific behavior can be challenging and time-consuming. Waiting for a constrained-random simulation to exercise the same behavior can also take a long time, with no guarantee that corner cases are really being exercised. In contrast, a formal verification tool can be very successful for finding difficult bugs. However, these tools are complex, they need huge resources (CPU time and memory), and they usually need specialized experts which limit their integration in the design flow. Recently, new formal and simulation based techniques has been developped to enhance the functional verification process. However, the rapid inreases in the design complexity makes it difficult to get rid of the presilicon bugs which have consistently increased for each new design generation. One way, to combat this verification bottlenck is to combine multiple, complementary techniques so that their combined strength is superior to the sum of the individual technques. In this research program, we address the development of hybrid verification tools and techniques to achieve the higher verification coverage of real-size microelectronics designs in a practical way. We believe that our approach will advance the state-of-the-art in systems verification, thus enhancing the shortening the design cycle. The direct beneficiary of this research will be the Canadian microelectronics industry. Furthermore, this proposal will contribute towards the training of a number of skilled personnel available to Canadian industry and academy.

当今的数字电路可能包含多达数亿个晶体管。人们认识到，功能验证仍然是设计过程的主要瓶颈，占其总成本的70％。通过模拟验证功能验证是一种通过得出功能测试（TestBench驱动程序）来查找错误的方法，同时尝试达到设计的功能覆盖目标。由于设计通过测试台驱动程序对设计的可控性有限，因此发现具有仿真的角错误通常是低效的。 撰写定向测试以行使特定的行为可能具有挑战性且耗时。等待限制的随机模拟行使相同的行为也可能需要很长时间，而不能保证实际行使角案件。相比之下，正式的验证工具对于寻找困难的错误可能非常成功。但是，这些工具很复杂，需要庞大的资源（CPU时间和内存），并且通常需要限制其在设计流中集成的专业专家。最近，已经开发了新的基于正式和模拟的技术来增强功能验证过程。但是，设计复杂性的快速散发使得很难摆脱每次新设计一代不断增加的Presilicon错误。与此验证瓶装作斗争的一种方法是结合多种互补技术，以便它们的组合强度优于单个技术的总和。在该研究计划中，我们探讨了混合验证工具和技术的开发，以实用的方式实现了实际尺寸的微电子设计设计的较高验证范围。我们认为，我们的方法将推进系统验证的最新方法，从而增强设计周期的缩短。这项研究的直接受益人将是加拿大微电子行业。此外，该建议将有助于培训加拿大工业和学院的许多熟练人员。