低消費電力デバイス向け化合物半導体と高誘電率絶縁膜及び金属電極の界面設計指針創出

为低功耗器件的化合物半导体、高介电常数绝缘膜和金属电极制定界面设计指南

• 批准号: 13J08817
• 负责人: ハサンザデ ダリューシュ
• 金额: $ 1.32万
• 依托单位: Tokyo Institute of Technology
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for JSPS Fellows
• 财政年份: 2013
• 资助国家: 日本
• 起止时间: 2013 至 2014
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-13J08817/
• 关键词: Atomic layer deposition; La203; InGaAs; MOSFET; Interface state traps; transconductance; 高誘電率絶膜; 界面準位; 熱安定性; 界面層

This research focuses on understanding and engineering the interface at high-k and InGaAs for enabling low power, high performance devices for application in mobile devices. Rare metal earth oxide La203 is chosen as the high-k oxide in this research. The main issues facing high-k/InGaAs interface, is the formation of unstable oxides which lead to formation of several types of defects such as interface traps (Dit) and bulk traps within both the oxide and substrate. However, it was found that extremely low defect interfaces can be fabricated by using La203 due to formation of LaInGaO interfacial layer. This interfacial layer has an amorphous nature and prevents the formation of unstable oxides, thus improving the quality of the interface. Lowest reported Dit on smallest equivalent oxide thickness on InGaAs substrates in the order of lower 10 to the power of 11 was reported by atomic layer deposition(ALD) of La203 on InGaAs conducted in this research. Due to prevalence of finFET design in … More recent devices structures, it is important to evaluate the characteristics of La203 interface on various orientations of InGaAs substrate. Contrary to a planar device structure, the device channel region in a FinFET device is composed of multiple orientations. Therefore, it is important to achieve high quality interface on all substrate orientations in order to benefit from the superior electrostatic gate properties of the finFET designs. In this research, MOSFETs with ALD-deposited La203 oxide on [100], [110] and [111] oriented InGaAs substrates were fabricated. All p-type substrates used in MOSFETs had pre-formed source and drain regions. It was found that a similiar Dit can be achieved on all substrates. The substhreshold swing in all MOSFETs was ~130 mV/dec which imply similar interface characteristics. However, higher drain current and transconductance values were achieved for the substrate with [111] orientation. This effect could be related to lower effective mass of electrons in this surface which is a material property of crystalline surface. These resutls show the potential for using La203 in various InGaAs devices in idustry. Less

这项研究重点是理解和工程High-K和Ingaas的界面，以实现低功率，高性能设备，用于在移动设备中应用。在这项研究中，选择稀有的金属氧化物LA203作为高K氧化物。高K/INGAAS界面面临的主要问题是形成不稳定的氧化物，这些氧化物导致形成几种类型的缺陷，例如氧化物和氧化物和底物内的界面陷阱（DIT）和散装陷阱。但是，发现可以使用Laingao界面层来制造极低的缺陷界面。该界面层具有无定形的性质，并防止了不稳定的氧化物的形成，从而提高了界面的质量。在这项研究中，LA203的原子层沉积（ALD）报告了在INGAAS底物上的最小氧化物厚度在INGAAS底物上的最低点的DIT。由于……较新的设备结构中的FinFET设计的普遍性，评估LA203界面在INGAAS底物的各种方向上的特征很重要。与平面设备结构相反，FinFET设备中的设备通道区域由多个方向组成。因此，重要的是要在所有底物方向上实现高质量的界面，以便从FinFET设计的上静电门特性中受益。在这项研究中，制造了[100]，[110]和[111]面向INGAAS底物的ALD沉积LA203氧化物的MOSFET。 MOSFET中使用的所有P型基材均具有预先形成的源和排水区域。发现可以在所有底物上实现一个相似的DIT。所有MOSFET中的threshord秋千为〜130 mV/dec，这意味着相似的界面特征。但是，以[111]取向实现了较高的漏极电流和转移值。这种效果可能与该表面中的电子有效质量较低有关，该表面是晶体表面的材料特性。这些重新灭绝显示了在思想中使用LA203在各种INGAAS设备中使用LA203的潜力。较少的

项目成果

Scalable La-silicate Gate Dielectric on InGaAs Substrate with High Thermal Stability and Low Interface State Densit

InGaAs 衬底上的可扩展硅酸铝栅极电介质，具有高热稳定性和低界面态密度

• 发表时间: 2013
• 作者: J. Naganawa;et al.;Daryoush Hassan Zadeh;Daryoush Hassan Zadeh
• 通讯作者: Daryoush Hassan Zadeh