LSI Test Technology for Evaluating Soft-Error-Rates in Combinational Logic Circuits

用于评估组合逻辑电路中软错误率的 LSI 测试技术

• 批准号: 18560359
• 负责人: KOBAYASHI Daisuke
• 金额: $ 2.34万
• 依托单位: Japan Aerospace Exploration Agency
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (C)
• 财政年份: 2006
• 资助国家: 日本
• 起止时间: 2006 至 2007
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-18560359/
• 关键词: Soft Errors; Single-Event Effects; Scan Designs; Design for Testability; Radiation; VLSIs; Combinational Circuits; SETs

Very large scale integrations, VLSIs, exhibit transient errors called "soft errors" when exposed to radiation environments. As a result of aggressive miniaturization of transistors, the soft error is now becoming a serious failure source of logic VLSIs like CPUs. It is thus desired to evaluate experimentally soft-error rates of fabricated logic chips in irradiation tests. For the purpose, we have developed a new LSI test technology in this research project.To evaluate soft-error rates of logic chips precisely, the following two requirements should he satisfied. Logic VLSIs consist of complicated networks of combinational logic circuits built with logic gates like inverters and sequential elements like flip-flops. It is required to count up the number of radiation-induced upsets of stored data at each sequential element scattered in the chips. Moreover, the data upsets are induced by not only direct radiation hits to the sequential elements and also latching pulse-type noises named "single-event transients, SETs, " which are generated by radiation hits to combinational logic circuits. The former is generally called "soft errors in sequential elements, " and the latter "soft errors in combinational logic circuits." It is now important to evaluate the impact of the soft errors in combinational logic circuits in particular. These both types of soft errors should be evaluated separately.Our test technology is based on the scan test technology, which is widely used in today's logic chips for testing their operations because it enables us to write and read each sequential element directly. We have developed a scan flip- flop circuit and an irradiation test method for the soft-error rates evaluation. We have experimentally demonstrated the validity of the technology. Moreover, we have successfully revealed detailed pulse-width distributions of SETs in SOI-CMOS logic gates, and developed a fast and accurate estimation technique of SET waveforms.

超大规模集成（VLSI）在暴露于辐射环境时会出现称为“软错误”的瞬态错误。由于晶体管的积极小型化，软错误现在正成为 CPU 等逻辑 VLSI 的严重故障源。因此，需要在辐照测试中通过实验来评估所制造的逻辑芯片的软错误率。为此，我们在本研究项目中开发了一种新的LSI测试技术。为了精确评估逻辑芯片的软错误率，需要满足以下两个要求。逻辑 VLSI 由复杂的组合逻辑电路网络组成，这些网络由逻辑门（如反相器）和时序元件（如触发器）构建。需要对散布在芯片中的每个顺序元素处的存储数据的辐射引起的翻转次数进行计数。此外，数据扰动不仅是由对顺序元件的直接辐射撞击引起的，而且还由称为“单事件瞬变，SET”的锁存脉冲型噪声引起，这些噪声是由对组合逻辑电路的辐射撞击产生的。前者通常被称为“顺序元件中的软错误”，后者被称为“组合逻辑电路中的软错误”。现在评估软错误对组合逻辑电路的影响尤其重要。这两种类型的软错误都应该单独评估。我们的测试技术基于扫描测试技术，该技术广泛应用于当今的逻辑芯片中，用于测试其操作，因为它使我们能够直接写入和读取每个顺序元素。我们开发了扫描触发器电路和辐照测试方法来评估软错误率。我们通过实验证明了该技术的有效性。此外，我们还成功揭示了SOI-CMOS逻辑门中SET的详细脉宽分布，并开发了一种快速、准确的SET波形估计技术。

项目成果

Estimation of single event transient voltage pulses in VLSI circuits from heavy-ion-induced transient currents measured in a single MOSFET

根据在单个 MOSFET 中测量的重离子感应瞬态电流来估计 VLSI 电路中的单事件瞬态电压脉冲

• 发表时间: 2007
• 作者: D.Kobayashi; et. al.
• 通讯作者: et. al.

Time-domain component analysis of heavy-ion-induced transient currents in fully-depleted SOI MOSFETs

全耗尽 SOI MOSFET 中重离子感应瞬态电流的时域分量分析

• 发表时间: 2006
• 作者: D.Kobayashi; et. al.
• 通讯作者: et. al.

単体トランジスタで観測された重イオン誘起過渡電流に基づくシングルイベント過渡電圧パルスの波形推定

基于在单个晶体管中观察到的重离子感应瞬态电流的单粒子瞬态电压脉冲的波形估计

• 发表时间: 2006
• 作者: 小林大輔; 他
• 通讯作者: 他

Estimation of single event transient voltage pulses in VLST circuits from heavy-ion-induced transients measured in a single MOSFET

根据在单个 MOSFET 中测量的重离子感应瞬态来估计 VLST 电路中的单事件瞬态电压脉冲

• 发表时间: 2007
• 作者: D.Kobayashi et al.

Time-domain component analysis of heavy-ion-induced transient currents in fully-depleted SOI MOSFETs

全耗尽 SOI MOSFET 中重离子感应瞬态电流的时域分量分析

• 发表时间: 2006
• 作者: D.Kobayashi et al.