Study on Fusion-neutron Damage Dynamics of Semiconductor Materials

半导体材料聚变-中子损伤动力学研究

基本信息

批准号：
05558068
负责人：
IIDA Toshiyuki
金额：
$ 6.66万
依托单位：
Osaka University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Developmental Scientific Research (B)
财政年份：
1993
资助国家：
日本
起止时间：
1993 至 1995
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-05558068/
关键词：
CMOS SRAMIC Neutron-induced Soft-error TRIM code Si-SSD DT-DD Neutron Damage Correlation Si (n, alpha) Mg Reaction Neutron Displacement Damage Bit Soft-error Cross Section Zheng Liモデル電子捕獲中心照射効果ダイナミクス原子弾き出し DT・DD中性子損傷相関係数荷電粒子輸

项目摘要

In order to examine the fusion neutron induced soft-error on memory ICs, several kinds of 1 Mbit CMOS SRAM ICs were irradiated with 14 MeV neutrons. Considering the cell population in the chip, we obtained the neutron susceptibility constant, i.e.bit soft-error cross section of 6-9*10^<-14> cm^2 for 1 Mbit CMOS SRAMs. This means that a soft-error is caused by neutron reactions in a limited region in a memory cell. The bit soft-error cross section value agreed roughly with that calculated by computer simulation with a Monte Carlo program based on the ion transport code TRIM-90 and the ENDF-B-VI neutron cross section data. Also we developed a special ion-beam apparatus for the examination of the soft-error mechanism.A silicon surface barrier detector (Si-SSD) was irradiated with neutrons from a deuteron accelerator. The leakage current increased proportionally with neutron fluence, which determined the neutron damage constant for the Si-SSD.The correlation factor of the DT and DD neutron damage in the Si-SSD was determined from the ratio of the DT and DD neutron damage constant and was found to be 2.3. We also calculated the rate of DT and DD neutron displacement damage for Si by using the TRIM-90 code and data on neutron reactions in the Si-SSD.The correlation factor of DT and DD neutron damage from the calculation agreed with that from the Si-SSD irradiation experiment.

为了检查聚变中子引起的存储 IC 软错误，用 14 MeV 中子辐照了几种 1 Mbit CMOS SRAM IC。考虑到芯片中的细胞群，我们获得了中子磁化率常数，即 1 Mbit CMOS SRAM 的位软错误截面为 6-9*10^<-14> cm^2。这意味着软错误是由存储单元中有限区域内的中子反应引起的。位软错误截面值与基于离子输运代码 TRIM-90 和 ENDF-B-VI 中子截面数据的蒙特卡罗程序计算机模拟计算出的值大致一致。我们还开发了一种特殊的离子束装置来检查软错误机制。硅表面势垒探测器（Si-SSD）被来自氘核加速器的中子照射。漏电流随中子注量成正比增加，从而决定了 Si-SSD 的中子损伤常数。Si-SSD 中 DT 和 DD 中子损伤的相关系数由 DT 和 DD 中子损伤常数的比值和结果发现为2.3。我们还利用 TRIM-90 程序和 Si-SSD 中子反应数据计算了 Si 的 DT 和 DD 中子位移损伤率。计算得出的 DT 和 DD 中子损伤相关系数与 Si 的相关系数一致-SSD辐照实验。