Research on high speed packet management with Reconfigurable Hardware

可重构硬件高速分组管理研究

基本信息

批准号：
15300013
负责人：
YAMAGUCHI Yoshinori
金额：
$ 7.87万
依托单位：
University of Tsukuba
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B)
财政年份：
2003
资助国家：
日本
起止时间：
2003 至 2006
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-15300013/
关键词：
Secure network Intrusion detection system FPGA Nondeterministic Finite Automaton encryption system IDS NFA DFA 侵入検地システムパケット

项目摘要

Attendant upon the acceleration of network, it is said to be difficult to develop network equipment which has the processing efficiency corresponding the speed of the network. In this research, we are going to develop network equipments which can accelerate the processing speed by using the rewritable semiconductor devices, such as FPGA.As the first topic, research and development of the network IDS ( Intrusion Detection System) is studied, especially the efficient execution scheme of the system using FPGA devices is pursued. The system firstly forms the finite-state machine from IDS patterns, next it is converted to hardware description language automatically. The research themes for this topic are to develop the efficient execution processing scheme based on the FPGA devices with regarding the reduction of the hardware quantity. Finally, IDS experimental system which exceeds 10Gbps was made, by using the IDS pattern matching circuit based on the nondeterministic finite automaton (NFA). On this system the reduction of the circuit scale of FPGA is also realized. Furthermore, in order to do the further reduction of the hardware quantity of the FPGA circuit, more research is pursued by adopting a data compression technique to the circuit design.As the second topic, we propose the reconfigurable system model which use FPGA to encrypt the data in the server-client encryption communication. In such a system, raising the availability of FPGA improves the performance. Therefore, it is important that the development of the prediction method to reducing useless reconfiguration of FPGA effectively. We propose the method of predicting the encryption algorithm used in the near future requests based on history of requests received so far to improve the efficiency of encryption. We employ the generalized n-gram model for that prediction, and verify its characteristics.

随着网络加速的服务员，据说很难开发具有处理效率的网络设备，这与网络速度相对应。在这项研究中，我们将开发网络设备，可以通过使用可重写的半导体设备（例如FPGA）来加速处理速度。作为第一个主题，研究和开发网络IDS（入侵检测系统），尤其是尤其是采用了使用FPGA设备的系统的有效执行方案。系统首先从IDS模式形成有限状态的机器，接下来，它将自动转换为硬件说明语言。该主题的研究主题是基于FPGA设备开发有效的执行处理方案，内容涉及减少硬件数量。最后，通过使用基于非确定性有限自动机（NFA）的IDS模式匹配电路，制造了超过10Gbps的IDS实验系统。在该系统上，还实现了FPGA电路尺度的降低。此外，为了进一步减少FPGA电路的硬件数量，通过对电路设计采用数据压缩技术来进行更多的研究。作为第二个主题，我们建议使用FPGA加密可重新配置的系统模型服务器客户加密通信中的数据。在这样的系统中，提高FPGA的可用性可提高性能。因此，重要的是，预测方法的发展有效地减少了无用的重新配置。我们提出了一种方法，可以根据迄今为止收到的请求的历史记录来预测在不久的将来请求中使用的加密算法，以提高加密效率。我们对该预测采用了广义的N-Gram模型，并验证其特征。