Modeling of GaN-based Electron Devices

GaN 基电子器件建模

基本信息

  • 批准号:
    14550329
  • 负责人:
  • 金额:
    $ 1.79万
  • 依托单位:
  • 依托单位国家:
    日本
  • 项目类别:
    Grant-in-Aid for Scientific Research (C)
  • 财政年份:
    2002
  • 资助国家:
    日本
  • 起止时间:
    2002 至 2004
  • 项目状态:
    已结题

项目摘要

Recently, GaN-based FETs have received great interest because of their potential applications to high power and high temperature microwave devices. However, slow current transients are often observed even if the drain voltage or the gate voltage is changed abruptly. This is called drain lag or gate lag, and is problematic in circuit applications. The slow transients mean that the dc I-V curves and the ac I-V curves become quite different, resulting in lower ac power available than that expected from the dc operation. This is called power slump or current collapse in the GaN-device field. These are regarded as trap-related, and there are many experimental works reported on these phenomena. But, few theoretical works have been reported for GaN-based FETsTherefore, in this work, two-dimensional transient simulations of GaN MESFETs have been performed in which a three level compensation model is adopted for the semi-insulating buffer layer where a shallow donor a deep donor, and a deep acc … More eptor are considered. Quasi-pulsed I-V curves have been derived from the transient characteristics. It has been shown that when the drain voltage is raised, the drain current overshoots the steady-state value, and when it is lowered, the drain current remains at a low value, showing drain-lag behavior. These are explained by the deep donor's electron capturing and electron emission processes. The drain lag has been shown to become a cause of current collapse, although some gate lag is also seen due to deep levels in the buffer layer. The current collapse has been shown to be more pronounced when the deep-acceptor density in the buffer layer is higher and when the off-state drain voltage is higher, because the trapping effects become more significant. These buffer-trapping effects may be similar to trapping effects in an undoped GaN layer in AlGaN/GaN HEMTs. It is concluded that to minimize the current collapse in GaN FETs, the (deep) acceptor density in the buffer layer should be made low. Less
最近,基于GAN的FET非常出色,因为它们对高功率和温度微波的效果也是如此,即使漏极电压或栅极电压在电路上也有问题,也观察到了缓慢的电流瞬变。应用程序。与陷阱相关,并在此报道了基于GAN的FETSOMENAMENOMENAN,因此在这项工作中,GAN MESFET的二维瞬态模拟具有三级补偿模型缓冲层浅层和深度ACT ...脉冲的I-V曲线已被视为瞬态特征。 ,表现出排水量的行为。当缓冲液中的深度密度更高时,要越来越多,因为诱捕效应更为重要结论是,为了最大程度地减少gan Fet中的当前崩溃,应使缓冲层中的(深)accettor密度低。

项目成果

期刊论文数量(16)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
Buffer-trapping effects on drain lag and power compression in GaN FET
  • DOI:
    10.1002/pssc.200461311
  • 发表时间:
    2005-05
  • 期刊:
  • 影响因子:
    0
  • 作者:
    K. Horio;K. Yonemoto
  • 通讯作者:
    K. Horio;K. Yonemoto
Deep-level effects on slow current transients and current collapse in GaN MESFETs
GaN MESFET 中慢电流瞬变和电流崩溃的深层次效应
Analysis of drain lag and power compression in GaN MESFET
GaN MESFET 漏极滞后和功率压缩分析
Y.Kazami, D.Kasai, Y.Mitani, K.Horio: "Simulation of Lag Phenomena and Pulsed I-V Curves of Compound Semiconductor FETs as Affected by Impact Ionization"Journal of Computational Electronics. Vol.2. 203-206 (2003)
Y.Kazami、D.Kasai、Y.Mitani、K.Horio:“受碰撞电离影响的化合物半导体 FET 的滞后现象和脉冲 I-V 曲线的模拟”计算电子学杂志。
  • DOI:
  • 发表时间:
  • 期刊:
  • 影响因子:
    0
  • 作者:
  • 通讯作者:
Numerical analysis of current transients and power slump in GaAs and GaN FETs
GaAs 和 GaN FET 中的电流瞬变和功率骤降的数值分析
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HORIO Kazushi其他文献

HORIO Kazushi的其他文献

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