Modeling of GaN-based Electron Devices

GaN 基电子器件建模

基本信息

批准号：
14550329
负责人：
HORIO Kazushi
金额：
$ 1.79万
依托单位：
Shibaura Institute of Technology
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (C)
财政年份：
2002
资助国家：
日本
起止时间：
2002 至 2004
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-14550329/
关键词：
GaN FET current collapse drain lag gate lag trap buffer layer device simulation MESFET HEMT

项目摘要

Recently, GaN-based FETs have received great interest because of their potential applications to high power and high temperature microwave devices. However, slow current transients are often observed even if the drain voltage or the gate voltage is changed abruptly. This is called drain lag or gate lag, and is problematic in circuit applications. The slow transients mean that the dc I-V curves and the ac I-V curves become quite different, resulting in lower ac power available than that expected from the dc operation. This is called power slump or current collapse in the GaN-device field. These are regarded as trap-related, and there are many experimental works reported on these phenomena. But, few theoretical works have been reported for GaN-based FETsTherefore, in this work, two-dimensional transient simulations of GaN MESFETs have been performed in which a three level compensation model is adopted for the semi-insulating buffer layer where a shallow donor a deep donor, and a deep acc … More eptor are considered. Quasi-pulsed I-V curves have been derived from the transient characteristics. It has been shown that when the drain voltage is raised, the drain current overshoots the steady-state value, and when it is lowered, the drain current remains at a low value, showing drain-lag behavior. These are explained by the deep donor's electron capturing and electron emission processes. The drain lag has been shown to become a cause of current collapse, although some gate lag is also seen due to deep levels in the buffer layer. The current collapse has been shown to be more pronounced when the deep-acceptor density in the buffer layer is higher and when the off-state drain voltage is higher, because the trapping effects become more significant. These buffer-trapping effects may be similar to trapping effects in an undoped GaN layer in AlGaN/GaN HEMTs. It is concluded that to minimize the current collapse in GaN FETs, the (deep) acceptor density in the buffer layer should be made low. Less

最近，基于GAN的FET由于对高功率和高温微波设备的潜在应用而引起了极大的兴趣。但是，即使漏极电压或栅极电压突然更换，通常也会观察到缓慢的电流瞬变。这称为排水滞后或门滞后，在电路应用中是有问题的。缓慢的瞬变意味着DC I-V曲线和AC I-V曲线变得截然不同，从而使AC功率较低，而AC功率较低。这称为gan设备场中的电力衰竭或电流崩溃。这些被认为是陷阱相关的，并且在这些现象上报告了许多实验性工作。但是，对于基于GAN的FETS，在这项工作中，几乎没有报道了基于GAN的FETS，进行了对GAN MESFET的二维瞬态仿真，在该工作中，对半绝缘缓冲层采用了三级补偿模型，其中浅层供体的浅层供体的深层供体和深度ACC…考虑了更多的eptor。准脉冲的I-V曲线是从瞬态特征得出的。已经显示的是，当升压电压升高时，排水电流过冲的稳态值，并且当降低时，漏极电流保持低值，显示了排水滞后的行为。这些用深供体的电子捕获和电子发射过程来解释。尽管由于缓冲层中的深度水平，但出现了一些栅极滞后，但排水滞后已被证明是当前塌陷的原因。当缓冲层中的深层密度较高，并且当阳离子漏极电压更高时，当前的崩溃已被证明更为明显。这些缓冲捕获效应可能类似于Algan/Gan Hemts中未掺杂的GAN层中的捕获效应。可以得出结论，要最大程度地减少GAN FET中的当前崩溃，应使缓冲层中的（深）受体密度低。较少的