Thermal Deformation Analysis of Electronic Packages by Moire Interferometry and Phase-Shifting Method

莫尔干涉和相移法对电子封装的热变形分析

基本信息

批准号：
13650091
负责人：
ARAKAWA Kazuo
金额：
$ 2.3万
依托单位：
Kyushu University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (C)
财政年份：
2001
资助国家：
日本
起止时间：
2001 至 2002
项目状态：
已结题

项目摘要

In the present research work, moire interferometry was applied to analyze thermal deformations of electronic packages, QFP (Quad Flat Package), MCM (Multi Chip Module) and FC (Flip-Chip Package). High-resolution moire interferometry was also developed to determine thermal displacements and strains of electronic packages, SOJ (Small Outline J-Leaded Package) and Stacked-MCP (Multi Chip Package). The conclusions from the present study can be summarized as follows.The thermal deformations of QFP and MCM packages measured by moire interferometry showed that high deformations occurred at the edges and corners of the chip. When the QFP was mounted on PWB (Printed Wiring Board), the deformations increased due to the influence of the substrate with high CTE (Coefficient of Thermal Expansion). It is also found that the number of chips and their locations in MCM greatly affected the package deformation.The thermal deformations of FCs were evaluated and the effects of underfill and substrate were … More investigated. The results showed that the underfill created similar curvatures between the chip and substrate. The multi-layer substrate decreased the CTE mismatch between the chip and substrate and the bending deformations of the packages. It is found that the thermal strains of solder balls were the smallest in the package underfilled and mounted on multi-layer substrate.Phase-shifting moire interferometry and digital image processing were developed and applied to nano-order resolution measurement in the displacements. The digital image processing made it possible to analyze the strain fields accurately.The phase-shifting method was also applied to the thermal deformation analyses of SOJ and Stacked-MCP. The results of the two packages showed that the normal strains were high at the ends of the chip, and the shear strain concentrated at the chip corners. The strain values in SOJ increased by about 50% when the package was mounted on PWB. In Stacked-MCP, the normal strain also concentrated at the interface of the two chips. The shear strain at the ends of the lower chip increased by about 76% with a temperature change of 25 deg.C. Less

在目前的研究工作中，莫尔干涉仪被应用于分析电子封装的热变形，还开发了QFP（四方扁平封装）、MCM（多芯片模块）和FC（倒装芯片封装）来确定。电子封装、SOJ（小外形 J 引线封装）和堆叠式 MCP（多芯片封装）的热位移和应变本研究的结论可以是：总结如下。通过莫尔干涉测量法测量QFP和MCM封装的热变形表明，芯片的边缘和拐角处发生了较大的变形。当QFP安装在PWB（印刷线路板）上时，由于影响而导致变形增加。还发现MCM中芯片的数量及其位置对封装变形有很大影响。对 FC 进行了评估，并研究了底部填充材料和基板的影响。结果表明，底部填充材料在芯片和基板之间产生了相似的曲率，从而减少了芯片和基板之间的 CTE 不匹配以及弯曲变形。研究发现，在底部填充并安装在多层基板上的封装中，焊球的热应变最小。相移莫尔干涉测量技术和数字图像处理技术被开发出来并应用于纳米级分辨率测量。数字图像处理使得精确分析应变场成为可能。相移方法也应用于SOJ和Stacked-MCP的热变形分析，这两种封装的结果表明法向应变较高。当封装安装在 PWB 上时，剪切应变集中在芯片角部，应变值增加了约 50%。两者中的温度变化 25 ℃ 时，下切屑末端的剪切应变增加约 76%。