A Study of a High-Speed and Highly-Functional Instruction Feeding Mechanism for the VLSI Architecture

VLSI体系结构的高速、高性能指令馈送机制的研究

• 批准号: 12680325
• 负责人: SUZUKI Ken-ichi
• 金额: $ 2.24万
• 依托单位: Miyagi National College of Technology (2001-2002)Tohoku University (2000)
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Scientific Research (C)
• 财政年份: 2000
• 资助国家: 日本
• 起止时间: 2000 至 2002
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-12680325/
• 关键词: Compute architecture; VLIW; Cache memory; Memory; VLIWアーキテクチャ; 命令発行機構; 命令キャッシュ; MULHIキャッシュ

The VLIW architecture, that is the most promising for the implementation of the next generation microprocessors, executes many instructions in parallel, requiring a high performance memory system to supply a huge number of instructions in short time from the main memory to its functional units. We introduce a high performance instruction cache mechanism devoted to the VLIW architecture, named the MULHI (MULtiple HIt) cache. A MULHI cache achieves high cache hit ratio by eliminating unnecessary "nop" instructions from its cache memory array, that enables to create a high-bandwidth memory system.The MULHI cache is based on the same concept with the COMPRESS cache and the SILO cache, at the point of eliminating nops from their data array. However, only the MULHI cache could apply a cache associativity to its cache management policy to acquire a higher cache hit ratio.Using software simulations, we evaluate the MULHI cache miss ratio that show it achieve a higher (OPC Operations Per Cycle) than the other cache mechanisms. Moreover, we make a detailed hardware design, that show the overhead of the MULHI cache control logic circuits is significantly small. Consequently, the MULHI cache architecture is much feasible for implementing a high speed memory system for VLIW processors.At last, as a new application of cache memory, we evaluate a real-time ray tracing system, that is remarkably powerful for rendering images.

VLIW体系结构是下一代微处理器实现的最有希望的架构，并并行执行许多指令，要求高性能内存系统在短时间内从主内存到其功能单元提供大量指令。我们介绍了专门针对VLIW体系结构的高性能指令缓存机制，名为Mulhi（多重命中）缓存。 Mulhi缓存通过从其高速缓存内存阵列中消除不必要的“ NOP”指令来达到高缓存的命中率，这使得Mulhi Cache基于与压缩缓存和Silo Cache相同的概念，并在消除从其数据驱动器中消除NOP的nop。但是，只有MULHI缓存才能将缓存关联应用于其高速缓存策略以获取更高的高速缓存命中率。使用软件模拟，我们评估了Mulhi Cache Miss比率，该比率表明其比其他缓存机制更高（OPC操作）。此外，我们进行了详细的硬件设计，以显示Mulhi Cache Control逻辑电路的开销非常小。因此，Mulhi缓存体系结构对于为VLIW处理器实现高速存储系统是可行的。最后，作为缓存内存的新应用，我们评估了一个实时射线跟踪系统，对于渲染图像非常有力。

项目成果

TADA Jubei, NAKAIKE Takuya, SUZUKI Ken-ichi, OOBA Nobuyuki, KOBAYASHI Hiroaki, NAKAMURA Tadao: "Design and Evaluation of the MULHI Cache"Transactions of the IEICE. J85-D-I, No.3. 274-285 (2002)

TADA Jubei、NAKAIKE Takuy​​a、SUZUKI Ken-ichi、OOBA Nobuyuki、KOBAYASHI Hiroaki、NAKAMURA Tadao：“MULHI 缓存的设计与评估”IEICE 的交易。

多田十兵衛, 沖池卓也, 鈴木健一, 大庭信之, 小林広明, 中村維男: "MULHIキャッシュの設計及び評価"電子情報通信学会論文誌 D-I. J85-D-I・3. 274-285 (2002)

Jubei Tada、Takuy​​a Okiike、Kenichi Suzuki、Nobuyuki Oba、Hiroaki Kobayashi、Tsuyoshi Nakamura：“MULHI 缓存的设计和评估”IEICE Transactions J85-D-I・3（2002）。

多田十兵衛, 中池卓也, 鈴木健一, 大庭信之, 小林広明, 中村維男: "MULHIキャッシュの設計及び評価"電子情報通信学会論文誌D-I. J85-D-I・3. 274-285 (2002)

Jubei Tada、Takuy​​a Nakaike、Kenichi Suzuki、Nobuyuki Oba、Hiroaki Kobayashi、Tsuyoshi Nakamura：“MULHI 缓存的设计和评估”IEICE Transactions J85-D-I・3（2002）。

鈴木健一, 斎田泰昌, 佐野健太郎, 大庭信之, 小林広明, 中村維男: "3DCGiRAMアーキテクチャによる実時間レイトレーシングシステム"電子情報通信学会論文誌 D-II. J85-D-II・8. 1365-1367 (2002)

Kenichi Suzuki、Yasumasa Saida、Kentaro Sano、Nobuyuki Oba、Hiroaki Kobayashi、Yoshio Nakamura：“使用 3DCGiRAM 架构的实时光线追踪系统”IEICE Transactions D-II·1365-1367 (2002)。

SUZUKI Ken-ichi, SAIDA Yasumasa, SANO Kentaro, OOBA Nobuyuki, KOBAYASHI Hiroaki, NAKAMURA Tadao: Transactions of the IEICE. J85-D-II, No.8. 1365-1367 (2002)

SUZUKI Ken-ichi、SAIDA Yasumasa、SANO Kentaro、OOBA Nobuyuki、KOBAYASHI Hiroaki、NAKAMURA Tadao：IEICE 交易。