Implementation of highly parallel signal processing system for multidimensional state-space digital filtering

多维状态空间数字滤波高度并行信号处理系统的实现

• 批准号: 03555067
• 负责人: KAWAMATA Masayuki
• 金额: $ 6.59万
• 依托单位: Tohoku University
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Developmental Scientific Research (B)
• 财政年份: 1991
• 资助国家: 日本
• 起止时间: 1991 至 1992
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-03555067/
• 关键词: Multidimensional digital filters; State-space model; Systolic array; Behavioral description language; VLSI processor

In this research, we design and evaluate highly parallel VLSI processors for real time 2-D state-space digital filters using hierarchical behavioral description language and synthesizer. The architecture of the 2-D state-space digital filtering system is a linear systolic array of homogeneous VLSI processors, each of which consists of eight processing elements (PEs) executing 1-D state-space digital filtering with multi-input and multi-output. HI-erarchical behavioral description language and synthesizer are adopted to design and evaluate PE's and the VLSI processors. One 16 bit fixed-point PE executing an (4,4)-th order 2-D state-space digital filtering is described on the basis of distributed arithmetic in about 1,200 steps by the description language and is composed of 15 K gates in terms of 2 input NAND gate. One VLSI processor which is a cascade connection of eight PEs is composed of 129 K gates and can be integrated into one 15 X 15 [mm^2] VLSI chip using 1 mum CMOS standard cell. The 2-D state-space digital filtering system composed of 128 VLSI processors at 25 MHz clock can execute a 1,024 X 1,024 image in 1.47 [m sec and thus can be applied to real-time conventional video signal processing.

在这项研究中，我们使用层次行为描述语言和合成器设计和评估实时2D状态空间数字过滤器的高度并行VLSI处理器。二-D状态空间数字过滤系统的架构是均匀VLSI处理器的线性收缩期数组，每个处理器都由八个处理元素（PES）组成，该元素（PES）执行具有多输入和多输出的1-D状态空间数字过滤。 HI-Erarchical行为描述语言和合成器用于设计和评估PE和VLSI处理器。一个16位固定点的PE执行（4,4）-Th顺序2-D状态空间数字过滤是根据分布式算术在约1,200个步骤中通过描述语言来描述的，并由2个输入NAND GATE的15 K门组成。一个VLSI处理器是八个PES的级联连接，由129 K大门组成，可以使用1 MMUM CMOS标准单元组整合到一个15 x 15 [mm^2] VLSI芯片中。由25 MHz时钟以128个VLSI处理器组成的二维状态空间数字过滤系统可以在1.47中执行1,024 x 1,024图像[M sec，因此可以应用于实时的常规视频信号处理。

项目成果

Takehiko Kagoshima, Masayuki Kawamata and Tatsuo Higuchi: "Design of three-dimensional for frequency domain specifications" Technical Report of Digital Signal Processing, IEICE. 55-62. (1992)

Takehiko Kagoshima、Masayuki Kawamata 和 Tatsuo Higuchi：“频域规范的三维设计”数字信号处理技术报告，IEICE。

岩田 靖,川又 政征,樋口 龍雄: "分母分離形2次元ディジタルフィルタのVLSI向きアーキテクチャ" 電子情報通信学会秋季大会講演論文集. 1. 106 (1992)

Yasushi Iwata、Masayuki Kawamata、Tatsuo Higuchi：“适用于分母分离二维数字滤波器的 VLSI 架构” IEICE 秋季会议论文集 1. 106 (1992)。

Tian-Bo Deng,Masayuki Kawamata: "Design of Separable-Denominator 2-D Digital Filters Using the Reduced-Dimensional Decomposition Model" Multidimensional Systems and Signal Processing. 3. 89-96 (1992)

邓天波，川俣雅之：“使用降维分解模型设计可分离分母二维数字滤波器”多维系统和信号处理。

岩田 靖,川又 政征,樋口 龍雄: "2次元状態空間ディジタルフィルタのVLSIプロセッサ設計" 電気関係学会東北支部連合大会予稿集. 342 (1991)

Yasushi Iwata、Masayuki Kawamata、Tatsuo Higuchi：“二维状态空间数字滤波器的VLSI处理器设计”日本电气工程师学会东北分会会议记录342（1991）。

Masayuki KAWAMATA,Takehiko KAGOSHIMA,Tatsuo HIGUCHI: "Design of Three-Dimensional Recursive Digital Filters Via Decomposition" Proc.of the Seventh Workshop on Multidimensional Signal Processing. 315 (1991)

Masayuki KAWAMATA、Takehiko KAGOSHIMA、Tatsuo HIGUCHI：“通过分解设计三维递归数字滤波器”第七届多维信号处理研讨会论文集。