Quantification of the Trade-off between Energy and Exactness in Computer Vision Processor Architectures Enhanced with Stochastic Computing Mechanisms

通过随机计算机制增强的计算机视觉处理器架构中能量与精确性之间权衡的量化

• 批准号: 279180031
• 负责人: Professor Dr.-Ing. Holger Blume
• 金额: --
• 依托单位: Abteilung Entwurf integrierter Systeme
• 依托单位国家: 德国
• 项目类别: Research Grants
• 财政年份: 2015
• 资助国家: 德国
• 起止时间: 2014-12-31 至 2018-12-31
• 项目状态: 已结题
• 来源: https://gepris.dfg.de/gepris/projekt/279180031?language=en
• 关键词: Quantification; Trade; off; between; Energy

Stochastic computing has recently emerged as a promising approach for designing energy-efficient embedded hardware systems, taking into account the ability of many applications (e.g., computer vision) to tolerate the loss of precision in the computed results. Rather than designing the hardware for worst case scenarios featuring expensive guard-bands, designers can relax the implementation constraints and deliberately expose hardware variability, obtaining significant processing performance improvements and energy benefits. Typical implementation constraints are related to operation frequency or operation voltage. Reducing the operation voltage will significantly reduce the power consumption and increase the error rate (i.e., malfunctioning). How to design "imprecise" hardware systems, in order to reduce the error rate while exposing hardware variability, is the main challenge of stochastic computing. Understanding all these hardware design trade-offs and their implication on the target application resulting from the imprecise computation is mandatory.The use of stochastic computing in processor architectures and computer vision applications requires the study of new hardware design techniques at all design levels (i.e., application, processor architecture, and chip layout). This project proposes to quantify the energy-exactness trade-offs in computer vision processor architectures enhanced with stochastic computing mechanisms. For this purpose, two different processor architectures (i.e., a VLIW architecture enhanced with SIMD instructions and a Vector Processor architecture), which orthogonally exploit the data parallelism inherent in computer vision algorithms will be studied. Different processing characteristics result in different hardware mechanisms that require different stochastic computing approaches in order to increase their performance and/or energy efficiency. Analytical error and power models of the resulting stochastic computing mechanisms will be derived to estimate the computation exactness and power consumption of both processor architectures, respectively. Moreover, FPGA-based rapid prototyping will be used to accelerate the verification and analysis of the processing performance of both processor architectures. Furthermore, the computation errors introduced by the stochastic mechanisms and the power consumption models, taking the internal switching activity into account, will be also emulated. Several feature extraction algorithms with different quality, reliability, and cost-effectiveness for object detection and tracking will be used to evaluate the influence of the stochastic computing errors. Finally, this project will allow not only to find and understand the optimal stochastic processor architecture for the exemplary feature extraction algorithm, but also to identify new stochastic computing mechanisms for different processor architecture types especially suited for computer vision applications.

考虑到许多应用程序（例如，计算机视觉）能够忍受计算结果中的精度丧失的能力，随机计算最近成为设计节能嵌入式硬件系统的有前途的方法。设计师可以放宽实施约束并故意揭示硬件可变性，从而获得大量的处理性能改善和能源益处，而不是为最坏情况设计硬件设计硬件，而是可以放松实施约束并故意暴露了硬件的可变性。典型的实现约束与操作频率或操作电压有关。降低操作电压将显着降低功耗并提高错误率（即故障）。如何设计“不精确”的硬件系统，以降低错误率，同时暴露硬件可变性，这是随机计算的主要挑战。强制了解所有这些硬件设计权衡及其对由于不准确计算而产生的目标应用的含义。该项目建议通过随机计算机制来量化计算机视觉处理器体系结构中的能量脱位权衡。为此，将研究两个不同的处理器体系结构（即，通过SIMD指令增强了VLIW体系结构和矢量处理器体系结构），它们将在正交方面利用计算机视觉算法中固有的数据并行性。不同的处理特性导致不同的硬件机制需要不同的随机计算方法，以提高其性能和/或能源效率。将得出所得随机计算机制的分析误差和功率模型，以分别估计两个处理器架构的精确性和功耗。此外，基于FPGA的快速原型将用于加速对两个处理器架构的处理性能的验证和分析。此外，还将模拟由随机机制和功耗模型引入的计算误差（考虑到内部切换活动）。具有不同质量，可靠性和对象检测和跟踪成本效益的几种特征提取算法将用于评估随机计算误差的影响。最后，该项目不仅允许为示例性特征提取算法找到并理解最佳的随机处理器体系结构，而且还可以识别针对不同处理器体系结构类型的新的随机计算机制，特别适合计算机视觉应用程序。

项目成果

A Coding Approach to Improve the Energy Efficiency of Approximate NoCs

• DOI: 10.1109/recosoc48741.2019.9034965
• 发表时间: 2019-07
• 期刊: 2019 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
• 作者: A. Najafi;Lennart Bamberg;G. P. Vayá;A. Ortiz

Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder

• DOI: 10.1109/tvlsi.2018.2822278
• 发表时间: 2018-04
• 期刊: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
• 影响因子: 2.8
• 作者: Ayad M. Dalloo;Ardalan Najafi;Alberto García-Ortiz

FPGA emulation methodology for fast and accurate power estimation of embedded processors

用于快速准确估计嵌入式处理器功耗的 FPGA 仿真方法

• DOI: 10.1016/j.sysarc.2016.12.008
• 发表时间: 2017
• 期刊: J. Syst. Archit.
• 作者: S. Hesselbarth;G. Schewior;H. Blume
• 通讯作者: H. Blume

Coherent Design of Hybrid Approximate Adders: Unified Design Framework and Metrics

混合近似加法器的相干设计：统一设计框架和指标

• DOI: 10.1109/jetcas.2018.2833284
• 发表时间: 2018
• 期刊: IEEE Journal on Emerging and Selected Topics in Circuits and Systems
• 影响因子: 4.6
• 作者: A. Najafi;M. Weissbrich;G. Paya-Vaya;A. Garcia-Ortiz
• 通讯作者: A. Garcia-Ortiz

Misalignment-aware delay modeling of narrow on-chip interconnects considering variability

考虑可变性的窄片上互连的未对准感知延迟建模

• DOI: 10.1109/mocast.2018.8376593
• 发表时间: 2018
• 期刊: 2018 7th International Conference on Modern Circuits and Systems Technologies (MOCAST)
• 作者: A. Najafi;L. Bamberg;A. Garcia-Ortiz
• 通讯作者: A. Garcia-Ortiz