CAREER: Building Scalable and Reliable Composable Computer Architectures

职业：构建可扩展且可靠的可组合计算机架构

• 批准号: 2341039
• 负责人: Hyeran Jeon
• 金额: $ 49.8万
• 依托单位: University of California - Merced
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2024
• 资助国家: 美国
• 起止时间: 2024-07-01 至 2029-06-30
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2341039&HistoricalAwards=false
• 关键词: CAREER; Building; Scalable; Reliable; Composable

In the post-Moore era, computing platforms have become more diverse and heterogeneous. With the evolution of packaging and interconnect technology, multiple computing and memory components are integrated into a single processor package. The high-bandwidth and coherent interconnects enable multiple accelerators and memory components on a platform together achieve server scale computing power. Though this new paradigm of computing platforms enables more optimal processor designs for domain-specific computing, the scalability is unclear. The fast interconnects between intra- and inter-chip components do not necessarily lead to linear speedup unless the communications are carefully handled. This project aims to keep up with performance projection of Moore’s law in post-Moore era with scalable architecture-level solutions. As graphics processing units (GPUs) are increasingly important for accelerating big data workloads, this project will focus on architecting highly scalable and reliable GPU platforms that can achieve almost linear speedup with the scaling of GPU chiplet modules and memory devices. The presented research tools and virtual memory systems will advance the state-of-the-art architectures with coherent and scalable communications among the intra- and inter-GPU chiplet components. The presented architecture design will be able to accelerate emerging big-data workloads without needing to access expensive cloud or data center supercomputers. The research findings will be incorporated into new and existing undergraduate and graduate courses as well as K-12 outreach programs.This project aims to address the following research questions: 1) How to manage all the integrated computing and memory components to communicate efficiently? Can the conventional virtual memory system handle large volumes of address translations? 2) How to achieve scalable and sustainable performance over multi-level non-uniform memory access (NUMA) architectures? Can consistent data access latency be enforced? This project answers these questions through two technical thrusts. The first thrust will design research tools that enable design explorations of scalable and heterogeneous platforms. Then, efficient virtual memory systems and page mapping algorithms will be architected. Unlike existing solutions, the methods presented in this project will exploit the unique GPU execution model while enabling coherent communication among intra- and inter-GPU packages. The second thrust will explore methods to enforce sustainable performance on the target multi-GPU systems having disaggregated memories. These new platforms have emerging challenges of deeper NUMA levels than conventional systems because individual computing and memory components can be integrated through multiple levels of extensible switches. This thrust will design efficient memory management and prefetch algorithms, which together enforce data to be ready within 1-2 NUMA distances.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

在后月时代，计算平台变得更加潜水和异质。随着包装和互连技术的演变，将多个计算和内存组件集成到单个处理器软件包中。高带宽和连贯的互连可在平台上启用多个加速器和内存组件共同实现服务器规模计算功率。尽管这种新的计算平台范式可以针对特定于域的计算进行更多最佳的处理器设计，但尚不清楚可扩展性。除非经过仔细处理，否则芯片间组件和芯片间组件之间的快速互连不一定会导致线性加速。该项目旨在通过可扩展的建筑级解决方案来跟上摩尔法律的绩效预测。由于图形处理单元（GPU）对于加速大数据工作负载越来越重要，因此该项目将着重于架构高度可扩展和可靠的GPU平台，这些平台可以通过GPU Chiplet模块和内存设备的缩放来实现几乎线性的加速。提出的研究工具和虚拟内存系统将在内部和GPU间芯片组件之间通过连贯且可扩展的通信来推进最先进的体系结构。提出的架构设计将能够加速出现的大数据工作负载，而无需访问昂贵的云或数据中心超级计算机。研究结果将纳入新的和现有的本科和研究生课程以及K-12外展计划中。该项目旨在解决以下研究问题：1）如何管理所有集成的计算和存储器组件以有效地交流？传统的虚拟内存系统可以处理大量地址翻译吗？ 2）如何在多级非均匀内存访问（NUMA）体系结构上实现可扩展和可持续性的性能？一致的数据访问延迟可以执行吗？该项目通过两个技术推力来回答这些问题。第一个推力将设计研究工具，以设计可扩展和异质平台的设计探索。然后，将构建有效的虚拟内存系统和页面映射算法。与现有的解决方案不同，本项目中介绍的方法将利用唯一的GPU执行模型，同时在内部和GPU软件包之间进行连贯的通信。第二个推力将探索在具有分离记忆的目标多GPU系统上实施可持续性能的方法。这些新平台比传统系统面临更深层次的NUMA级别的紧急挑战，因为可以通过多个可扩展开关进行集成单个计算和内存组件。这一推力将设计有效的内存管理和预取算法，这些算法共同执行数据在1-2个NUMA距离内准备就绪。该奖项反映了NSF的法定任务，并通过使用基金会的知识分子的优点和更广泛的影响来评估NSF的法定任务，并被认为是诚实的支持。