CRII: SHF: A Flexible, Learning-Enabled, and Multi-layer Interconnection Architecture for Optimized On-Chip Communications

CRII：SHF：一种灵活的、支持学习的多层互连架构，用于优化片上通信

• 批准号: 2245950
• 负责人: Ke Wang
• 金额: $ 17.47万
• 依托单位: University of North Carolina at Charlotte
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2023
• 资助国家: 美国
• 起止时间: 2023-05-01 至 2025-04-30
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2245950&HistoricalAwards=false
• 关键词: CRII; SHF; Flexible; Learning; Enabled

The rapid scaling of technology has led to the growth of parallel systems that integrate an increased number of cores per chip. For contemporary computer systems, this trend has signified a paradigm shift from computation-centric to communication-centric design methodologies. Consequently, enhancing security, reliability, performance, and energy efficiency of Network-on-Chips (NoCs) architectures is proving to be one of the most critical design challenges to realizing the performance potential of future parallel systems. Despite existing NoC research having made significant progress addressing individual design objectives, relatively few efforts to date have targeted all four challenges in a holistic manner due to the existence of design trade-offs and the complexity of dynamic interactions among various NoC hardware. For example, deploying per-router error correction circuit can lead to excessive delays and increased power consumption while recovering from the fault. Additionally, utilizing regional routing methods for security purposes may result in network hotspots and congestion that greatly hinder performance and lead to faults. Therefore, there is an imminent need for an optimized NoC design that manages the dynamic interactions and handles design trade-offs.This project devotes to developing a holistic design methodology that addresses the security and reliability of the entire NoC, while maximizing performance and energy efficiency. To achieve this, the project first carries out a thorough study of NoC fault mechanisms and security vulnerabilities. A variety of security-enhancing and fault-tolerant techniques are developed and investigated in order to assess their performance and overheads. Second, it develops a comprehensive and flexible NoC design framework that integrates multiple reconfigurable hardware with embedded NoC enhancement techniques to protect the NoC from transient and permanent faults and security vulnerabilities while meeting power and performance requirements. The designed framework incorporates a learning-enabled controller that deploys machine learning algorithms, such as supervised learning and reinforcement learning, to accurately capture the runtime behaviors of NoCs, model dynamic interactions, and handle trade-offs by automatically deploying the most suitable configurations of the dynamic hardware with the goal of maximizing system-level security, reliability, power, and performance. Finally, the project develops a cycle-accurate simulation tool and an FPGA prototype to evaluate the designed NoC framework. The holistic design approach, covering the NoC architecture designs and the machine learning techniques, will benefit future multicore architectures with improvements in security, dependability, energy efficiency, and performance.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

技术的快速扩展导致并行系统的发展，每个芯片集成的内核数量不断增加。对于当代计算机系统来说，这种趋势标志着从以计算为中心的设计方法到以通信为中心的设计方法的范式转变。因此，增强片上网络 (NoC) 架构的安全性、可靠性、性能和能源效率被证明是实现未来并行系统性能潜力的最关键的设计挑战之一。尽管现有的片上网络研究在解决个别设计目标方面取得了重大进展，但由于设计权衡的存在以及各种片上网络硬件之间动态交互的复杂性，迄今为止，以整体方式应对所有四个挑战的努力相对较少。例如，部署每个路由器的纠错电路可能会导致从故障中恢复时出现过度延迟并增加功耗。此外，出于安全目的而使用区域路由方法可能会导致网络热点和拥塞，从而极大地影响性能并导致故障。因此，迫切需要一种优化的片上网络设计来管理动态交互并处理设计权衡。该项目致力于开发一种整体设计方法，解决整个片上网络的安全性和可靠性，同时最大限度地提高性能和能效。为了实现这一目标，该项目首先对NoC故障机制和安全漏洞进行了深入研究。人们开发并研究了各种增强安全性和容错的技术，以评估其性能和开销。其次，它开发了全面且灵活的NoC设计框架，将多个可重构硬件与嵌入式NoC增强技术集成在一起，以保护NoC免受暂时性和永久性故障以及安全漏洞的影响，同时满足功耗和性能要求。设计的框架包含一个支持学习的控制器，该控制器部署监督学习和强化学习等机器学习算法，以准确捕获片上网络的运行时行为、建模动态交互，并通过自动部署最合适的网络配置来处理权衡。动态硬件，目标是最大限度地提高系统级安全性、可靠性、功率和性能。最后，该项目开发了一个周期精确的仿真工具和一个 FPGA 原型来评估设计的 NoC 框架。涵盖NoC架构设计和机器学习技术的整体设计方法将有利于未来的多核架构，提高安全性、可靠性、能源效率和性能。该奖项反映了NSF的法定使命，并通过评估被认为值得支持基金会的智力价值和更广泛的影响审查标准。

项目成果

FDMAX: An Elastic Accelerator Architecture for Solving Partial Differential Equations

FDMAX：用于求解偏微分方程的弹性加速器架构

• DOI: 10.1145/3579371.3589083
• 发表时间: 2023-06
• 期刊: Proceedings International Symposium on Computer Architecture
• 作者: Li, Jiajun;Zhang, Yuxuan;Zheng, Hao;Wang, Ke
• 通讯作者: Wang, Ke

Morph-GCNX: A Universal Architecture for High-Performance and Energy-Efficient Graph Convolutional Network Acceleration

Morph-GCNX：高性能、高能效图卷积网络加速的通用架构

• DOI: 10.1109/tsusc.2023.3313880
• 发表时间: 2024-03-01
• 期刊: IEEE Transactions on Sustainable Computing
• 影响因子: 3.9
• 作者: Ke Wang;Hao Zheng;Jiajun Li;A. Louri
• 通讯作者: A. Louri