Collaborative Research: CMOS+X: A Device-to-Architecture Co-development and Demonstration of Large-scale Integration of FeFET on CMOS for Emerging Computing Applications

合作研究：CMOS X：用于新兴计算应用的 CMOS 上大规模集成 FeFET 的设备到架构联合开发和演示

• 批准号: 2318808
• 负责人: Kai Ni
• 金额: $ 24万
• 依托单位: Rochester Institute of Tech
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2023
• 资助国家: 美国
• 起止时间: 2023-09-01 至 2024-04-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2318808&HistoricalAwards=false
• 关键词: Collaborative; Research; CMOS+X; Device; Architecture

In the new era of AI, modern computing electronics are facing tremendous challenges when a large amount of computing tasks, e.g. robotics, AR/VR, autonomous driving, require supports of gigantic computing models and enormous computing workloads. Such demands have dwarfed the capabilities of existing electronic hardware. As CMOS technology approaches 1 nm node, it is obvious that the conventional technology scaling will soon run out of steam to meet the ever-growing demand of computing power. To continue the Moore’s law, HfO2 based ferroelectric field effect transistor (FeFET) is one of the leading candidates with benefits of combined nonvolatility, high energy efficiency, and compatibility with CMOS. While many device-level developments have been performed on FeFET, one of the hindering factors is that the device’s development is often performed at small scale without high-level integration with CMOS technology, which is necessary to deliver a complete integrated-circuit (IC) solution for supporting the modern computing tasks. To overcome the limitation of existing developments, this proposal will develop cross-layer techniques from device to circuit and architecture enabling large-scale integration of the highly promising FeFET device with standard CMOS technology. This project will perform full-stack developments from device to architecture for the integration of CMOS and FeFET technology targeting emerging computing applications. Fabricated FeFET with CMOS at advanced technology nodes at a large scale will be used to demonstrate the proposed techniques. More specifically, we will perform the following developments. At device level, improved process for integration between nFeFET, pFeFET and CMOS will be developed allowing better technology fusion of the FeFET and CMOS devices; At design methodology, a joint device-circuit collaborative design flow will be developed to tailor the FeFET technology towards the need of emerging computing applications such as AI; Furthermore, novel circuit and architecture utilizing FeFET as both memory and computing devices will be developed to exploit the features of FeFET and its co-existence with CMOS technology; Finally, demonstrations on complex processors and accelerators for emerging applications, with joint CMOS and FeFET technology will be delivered to showcase the benefits of the emerging device integrated with CMOS. The integrative approach and demonstration of CMOS and FeFET fusion will manifest the system perspective of FeFET devices and establish a solid foundation for the future FeFET developments especially for the emerging computing tasks. By integrating the advanced semiconductor technology with emerging computing tasks, the proposed projects provide strong educational materials and opportunities for students to learn the multi-disciplinary developments of modern computing techniques and microelectronic devices. Both course materials and workshops on frontier semiconductor and computing techniques will be developed to provide solid training to the society while also promoting diversity and inclusion to college STEM education.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

在AI的新时代，现代计算电子设备在大量计算任务（例如机器人技术，AR/VR，自动驾驶，需要支持巨大的计算模型和巨大的计算工作负载。这种需求使现有电子硬件的功能相形见war。随着CMOS技术接近1 nm节点，很明显，常规技术扩展很快就会耗尽蒸汽，以满足计算能力不断增长的需求。为了继续《摩尔定律》，基于HFO2的铁电场效应变压器（FEFET）是领先的候选者之一，具有联合不易挥发性，高能效和与CMOS的兼容性的好处。尽管在FEFET上进行了许多设备级别的开发，但阻碍的因素之一是，该设备的开发通常是小规模执行的，而没有与CMOS技术的高级集成，这对于提供支持现代计算任务的完整集成电路（IC）解决方案是必不可少的。为了克服现有发展的局限性，该提案将开发从设备到电路和体系结构的跨层技术，从而使高度承诺的FEFET设备与标准CMOS技术的大规模集成。该项目将对从设备到体系结构进行全堆栈开发，以集成CMOS和FEFET技术，以新兴计算应用程序为目标。在大规模的高级技术节点上使用CMO制造的FEFET将用于演示所提出的技术。更具体地说，我们将执行以下发展。在设备级别，将开发NFEFET，PFEFET和CMO之间集成的过程改进，从而可以更好地融合FEFET和CMOS设备的技术融合；在Design方法论中，将开发一个联合设备电路协作设计流，以根据AI等新兴计算应用程序来定制FEFET技术；此外，将开发FEFET作为内存和计算设备的新型电路和建筑，以探索FEFET的功能及其与CMOS技术的共存。最后，将提供有关新兴应用程序的复杂处理器和加速器的演示，并将提供联合CMOS和FEFET技术，以展示与CMO集成的新兴设备的好处。 CMO和FEFET融合的综合方法和演示将展示FEFET设备的系统观点，并为未来的FEFET开发建立坚实的基础，尤其是对于新兴的计算任务。通过将先进的半导体技术与新兴的计算任务相结合，这些项目为学生提供了强大的教育材料和机会，以学习现代计算技术和微电子设备的多学科发展。在边境半导体和计算技术上的课程材料和讲习班都将开发为向社会提供良好的培训，同时还促进了对大学STEM教育的多样性和包容性。该奖项反映了NSF的法定任务，并被认为是通过基金会的知识分子优点和更广泛影响的审查标准来通过评估来获得的支持。