SBIR Phase I: Security Evaluation Platform for Automating Inclusion of Hardware Security in Integrated Circuit Design

SBIR 第一阶段：自动将硬件安全纳入集成电路设计的安全评估平台

• 批准号: 2126885
• 负责人: Mahdi Orooji
• 金额: $ 25.6万
• 依托单位: SECURESEMI CORPORATION
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2021
• 资助国家: 美国
• 起止时间: 2021-11-15 至 2022-10-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2126885&HistoricalAwards=false
• 关键词: SBIR; Phase; Security; Evaluation; Platform

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase I project is to secure Integrated Circuit (IC) Intellectual Property (IP) against untrusted parties in the globalized IC supply chain. Outsourcing of IC foundries creates risks of IC reverse engineering, overproduction, theft, and even piracy. A promising method of achieving hardware IP security is by logically locking the functionality of a design by replacing a subset of the design components with programmable elements. The correct content of these elements forms the key for unlocking/activation of the design in a secure facility and/or via a secure protocol after manufacturing. A technical challenge in commercializing this technology is the long time period typically needed to assess the security of a locked design against state-of-the-art attack algorithms at the design phase. This project will address this technical challenge by developing an Artificial Intelligence (AI)-assisted design security analyzer tool to instantaneously provide an accurate attack runtime estimation on a locked design, significantly reducing the design time.This Small Business Innovation Research (SBIR) Phase I project will significantly shorten the time required to assess attack resiliency of an obfuscated (locked) Integrated Circuit (IC) design. Running the state-of-the-art Boolean Satisfiability solvers (SAT attack) on a state-of-the-art computer server to de-obfuscate a locked design can take time - ranging from days to months. Such a long security analysis time is prohibitive for deployment in the design process where iterative design optimizations are needed for making power, performance, area, and security (PPAS) trade-offs. This project aims to address this challenge by introducing a novel approach that will bring the security assessment time down to near zero using a machine-learning based model. Based on recent advancements in graph and geometric deep learning techniques, an innovative end-to-end security assessment framework is proposed that directly and losslessly ingests the original design as a graph-structured input, and then automatically learns the discriminative features that influence logic locking security. To support sufficient data for the proposed data-driven method, a logic locking macro-database will be developed that encompasses the required PPAS, attack and defense information.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

这项小型企业创新研究（SBIR）I阶段项目的更广泛的影响/商业潜力是确保全球化IC供应链中的不受信任的政党确保综合电路（IC）知识产权（IP）。 IC铸造厂的外包会产生IC逆向工程，过度生产，盗窃甚至海盗的风险。实现硬件IP安全性的一种有希望的方法是通过逻辑地锁定设计的功能，通过用可编程元素替换设计组件的子集。这些元素的正确内容构成了在安全设施中解锁/激活设计后和/或通过安全协议解锁/激活的关键。商业化这项技术的技术挑战通常是在设计阶段评估针对最先进的攻击算法的锁定设计安全性所需的长期挑战。该项目将通过开发人工智能（AI）支持的设计安全分析仪工具来应对这一技术挑战，以立即提供对锁定设计的准确攻击运行时估计，从而大大缩短了设计时间。该小型企业创新研究（SBIR）I期项目将大大缩短OBFUSCECTECTECTECTECTECTER（ICLUSCED）的攻击（iC）（iC）的指定所需的时间。在最先进的计算机服务器上运行最先进的布尔值满意度求解器（SAT攻击），以消除锁定的设计可能需要时间 - 从几天到几个月不等。在设计过程中，在设计过程中需要进行迭代设计优化以进行电力，性能，区域和安全性（PPAS）权衡，因此在设计过程中进行了如此长的安全分析时间。该项目旨在通过引入一种新颖的方法来应对这一挑战，该方法将使用基于机器学习的模型将安全评估时间降至零接近零。根据图形和几何深度学习技术的最新进展，提出了创新的端到端安全评估框架，直接无损地将原始设计作为图形结构化输入摄入，然后自动学习影响逻辑锁定安全性的歧视性功能。为了支持拟议的数据驱动方法的足够数据，将开发一个逻辑锁定宏观数据库，涵盖所需的PPA，攻击和国防信息。该奖项反映了NSF的法定任务，并被认为是值得通过基金会的知识分子优点和更广泛影响的审查标准来通过评估来支持的。