SHF: Small: Next-Generation Fully Integrated Power Management Circuits: Enabling Faster and More Efficient Computing and Communication in Smaller and Lower-Cost Mobile Electronics

SHF：小型：下一代全集成电源管理电路：在更小、更低成本的移动电子产品中实现更快、更高效的计算和通信

• 批准号: 2007154
• 负责人: Cheng Huang
• 金额: $ 50万
• 依托单位: Iowa State University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2020
• 资助国家: 美国
• 起止时间: 2020-10-01 至 2024-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2007154&HistoricalAwards=false
• 关键词: SHF; Small; Next; Generation; Fully

The semiconductor industry has increasing demands for faster and more efficient computing and communication with next-generation System-on-Chips (SoCs) and 5G new radios in thinner, smaller and lower-cost devices. The existing Power Management Integrated Circuits (PMICs), which are essential to supply power to different system components, cannot keep up with the needs of future applications, and become the most significant bottleneck in system development in respect of speed, form-factor and cost. This project aims to develop new designs of high-frequency voltage regulators fully integrated with all the components, including power inductors and capacitors, embedded in the integrated circuit package. The dynamic speed will be enhanced to enable optimal power-saving strategies for SoCs, which are essential to relax power and thermal constraints for higher performance. The enhanced speed will enable high-bandwidth envelop-tracking techniques, which will greatly reduce the power overhead in supplying radio-frequency power amplifiers in high-speed communication systems and improve the overall efficiency. The form factor and cost will be dramatically reduced. Besides, since power supply is fundamental in any electronic device, this project will potentially benefit a wide range of scientific, industrial, and medical applications. In addition, the research, education and outreach activities will also contribute to training the future science and engineering workforce and broadening participation in STEM areas.To accomplish the research goal, this project will develop fully integrated voltage regulators with multiple innovations, e.g., 1) new power inductors: develop near-free and high-quality power inductors with in-package parasitics to enable the freedom to expand the number of phases for faster speed, higher power capacity and better efficiency without increasing the form-factor and cost; 2) new topologies and design strategies: a) develop maximum efficiency-tracking strategies to determine the optimal number of phases at the design stage, as well as in operation; b) develop multi-level topologies for one-stage voltage conversion directly from the battery to the load; 3) new controller and circuits: a) push the small-signal bandwidth to the theoretical limit by developing a self-learning compensator; b) maximize the large-signal speed by developing a smart hybrid array and a burst-mode operation; c) design control and circuit techniques to switch the multi-phase and multi-level power stages with optimal efficiency; d) develop dynamic voltage stress management for stacking and multi-level topologies to support a wide voltage range with ensured reliability under high-frequency and high-current operations. The designs will be realized in silicon and measured with detailed performance characterizations.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

半导体行业对更薄、更小、成本更低的设备中的下一代片上系统 (SoC) 和 5G 新无线电的更快、更高效的计算和通信的需求日益增长。现有的电源管理集成电路（PMIC）是为不同系统组件供电所必需的，但无法跟上未来应用的需求，成为系统开发在速度、外形尺寸和成本方面的最大瓶颈。该项目旨在开发高频稳压器的新设计，与嵌入集成电路封装中的所有组件（包括功率电感器和电容器）完全集成。动态速度将得到增强，以实现 SoC 的最佳节能策略，这对于放松功耗和热限制以获得更高的性能至关重要。速度的提高将使高带宽包络跟踪技术成为可能，这将大大降低高速通信系统中射频功率放大器的功率开销，并提高整体效率。外形尺寸和成本将显着降低。此外，由于电源是任何电子设备的基础，因此该项目将有可能使广泛的科学、工业和医疗应用受益。此外，研究、教育和推广活动还将有助于培训未来的科学和工程人员并扩大对 STEM 领域的参与。为了实现研究目标，该项目将开发具有多项创新的全集成电压调节器，例如 1)新型功率电感器：开发具有封装内寄生效应的近乎自由的高质量功率电感器，以便能够自由扩展相数，从而在不增加外形尺寸和成本的情况下实现更快的速度、更高的功率容量和更高的效率； 2) 新的拓扑和设计策略： a) 制定最大效率跟踪策略，以确定设计阶段以及运行中的最佳相数； b) 开发多级拓扑结构，用于直接从电池到负载的一级电压转换； 3）新的控制器和电路：a）通过开发自学习补偿器将小信号带宽推向理论极限； b) 通过开发智能混合阵列和突发模式操作来最大化大信号速度； c) 设计控制和电路技术，以最佳效率切换多相和多级功率级； d) 开发用于堆叠和多电平拓扑的动态电压应力管理，以支持宽电压范围，并在高频和大电流操作下确保可靠性。这些设计将在硅中实现，并通过详细的性能特征进行测量。该奖项反映了 NSF 的法定使命，并通过使用基金会的智力价值和更广泛的影响审查标准进行评估，被认为值得支持。

项目成果

A Fully In-Package 4-Phase Fixed-Frequency DAB Hysteretic Controlled DC-DC Converter with Enhanced Efficiency, Load Regulation and Transient Response

具有增强效率、负载调节和瞬态响应的全封装 4 相固定频率 DAB 迟滞控制 DC-DC 转换器

• DOI: 10.1109/cicc53496.2022.9772798
• 发表时间: 2022-04
• 期刊: 2022 IEEE Custom Integrated Circuits Conference (CICC
• 作者: Zhao, Lei;Tang, Junyao;Huang, Cheng
• 通讯作者: Huang, Cheng

Analytical Comparison of 3-Level 2-Phase and Double-Step-Down Topologies for Integrated High-Ratio DC-DC Converters in BCD and GaN Process

BCD 和 GaN 工艺中集成高比率 DC-DC 转换器的 3 级 2 相和双降压拓扑的分析比较

• DOI: 10.1109/ecce50734.2022.9947818
• 发表时间: 2022-10
• 期刊: 2022 IEEE Energy Conversion Congress and Exposition (ECCE
• 作者: Khan, Muhammad Rizwan;Zhang, Xin;Huang, Cheng
• 通讯作者: Huang, Cheng