SHF: Small: Collaborative Research: Multi-level Non-volatile FPGA Synthesis to Empower Efficient Self-adaptive System Implementations
SHF:小型:协作研究:多级非易失性 FPGA 综合,实现高效自适应系统
基本信息
- 批准号:1820537
- 负责人:
- 金额:$ 12.2万
- 依托单位:
- 依托单位国家:美国
- 项目类别:Standard Grant
- 财政年份:2017
- 资助国家:美国
- 起止时间:2017-08-01 至 2020-07-31
- 项目状态:已结题
- 来源:
- 关键词:
项目摘要
Self-adaptivity is a key requirement for many electronic devices to consistently interact with the dynamic, uncertain, and noisy physical environment. While Field Programmable Gate Arrays (FPGAs), being reconfigurable, are a natural platform for implementing such devices, it is becoming more and more difficult for traditional FPGAs to keep up with the ever-increasing scale and complexity of self-adaptive applications due to the limited scalability, high leakage power, and severe process variations of CMOS technologies. A set of prior research projects demonstrated that it is technically feasible to construct FPGAs based on non-volatile memories (NVMs). These NV-FPGAs offer attractive features such as better scalability, superior energy efficiency, near-zero power-on delay, anti-radiation, as well as the ability to store more than one bit per cell. However, NV-FPGAs also display a complex design space involving information density, read and write speeds, data retention time, and device endurance. When used for self-adaptive systems, the distinctive NVM characteristics may influence reconfiguration speed, clock frequency, circuit functionality, memory performance, and/or device lifetime.This project addresses this technology gap as it prepares NV-FPGAs for more demanding self-adaptive systems. This project aims to fine-tune various procedures on the FPGA synthesis flow based on NVM characteristics, so as to exploit their advantages and mitigate their shortcomings. First, considering the needs of self-adaptive applications, this project fine-tunes various steps on the FPGA synthesis flow. Novel techniques are proposed to optimize task scheduling, data allocation, logic mapping, placement, and routing to improve reconfiguration speed, energy efficiency, reliability, and endurance of NVM FPGAs. Second, this project explores the rich NVM design space and sets different optimization goals for look-up tables, flip-flops, and on-chip memories. The success of this project will lead to a long-lasting, rapid-adaptive, reliable, and energy-efficient platform better suited to the needs of a wide range of applications with self-adaptivity requirement, including healthcare, wellness, industry, and even military applications, all of which are critical for the United States to drive its new strategies of innovation and technology. It will also train a diverse type of engineers to design the future generation of embedded and cyber-physical systems with the cutting-edge technology of non-volatile memories. Algorithms and tools developed in this project will be made publicly available so that they will benefit the entire scientific community.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
自适应是许多电子设备与动态、不确定和嘈杂的物理环境持续交互的关键要求。虽然可重构的现场可编程门阵列 (FPGA) 是实现此类设备的自然平台,但传统 FPGA 越来越难以跟上自适应应用不断增长的规模和复杂性,因为CMOS 技术的可扩展性有限、漏电功率高以及工艺变化严重。一系列先前的研究项目表明,基于非易失性存储器(NVM)构建 FPGA 在技术上是可行的。这些 NV-FPGA 具有多种极具吸引力的特性,例如更好的可扩展性、卓越的能效、接近零的开机延迟、抗辐射以及每个单元存储多位的能力。然而,NV-FPGA 还表现出复杂的设计空间,涉及信息密度、读写速度、数据保留时间和设备耐用性。当用于自适应系统时,独特的 NVM 特性可能会影响重新配置速度、时钟频率、电路功能、存储器性能和/或器件寿命。该项目解决了这一技术差距,因为它为 NV-FPGA 准备了更苛刻的自适应系统系统。本项目旨在根据NVM特性对FPGA综合流程上的各个流程进行微调,以发挥其优点,弥补其缺点。首先,考虑到自适应应用的需求,本项目对FPGA综合流程的各个步骤进行了微调。提出了优化任务调度、数据分配、逻辑映射、布局和布线的新技术,以提高 NVM FPGA 的重新配置速度、能源效率、可靠性和耐用性。其次,该项目探索了丰富的NVM设计空间,并为查找表、触发器和片上存储器设定了不同的优化目标。该项目的成功将带来一个持久、快速自适应、可靠和节能的平台,更好地满足具有自适应要求的广泛应用的需求,包括医疗保健、健康、工业,甚至军事应用,所有这些对于美国推动其创新和技术新战略都至关重要。它还将培训各类工程师,利用非易失性存储器的尖端技术设计下一代嵌入式和网络物理系统。该项目开发的算法和工具将公开,以便使整个科学界受益。该奖项反映了 NSF 的法定使命,并通过使用基金会的智力价值和更广泛的影响审查标准进行评估,被认为值得支持。
项目成果
期刊论文数量(0)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
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Jingtong Hu其他文献
Invited:Hardware-aware Real-time Myocardial Segmentation Quality Control in Contrast Echocardiography
邀请:超声心动图中的硬件感知实时心肌分割质量控制
- DOI:
10.1109/dac18074.2021.9586158 - 发表时间:
2021-09-14 - 期刊:
- 影响因子:0
- 作者:
Dewen Zeng;Yukun Ding;Haiyun Yuan;Meiping Huang;Xiaowei Xu;Zhuang Jian;Jingtong Hu;Yiyu Shi - 通讯作者:
Yiyu Shi
Achieving Fairness Through Channel Pruning for Dermatological Disease Diagnosis
皮肤病诊断渠道修剪实现公平
- DOI:
10.48550/arxiv.2405.08681 - 发表时间:
2024-05-14 - 期刊:
- 影响因子:0
- 作者:
Qingpeng Kong;Ching;Dewen Zeng;Yu;Tsung;Jingtong Hu;Yiyu Shi - 通讯作者:
Yiyu Shi
Development of A Real-time POCUS Image Quality Assessment and Acquisition Guidance System
实时 POCUS 图像质量评估和采集引导系统的开发
- DOI:
10.48550/arxiv.2212.08624 - 发表时间:
2022-12-16 - 期刊:
- 影响因子:0
- 作者:
Zhenge Jia;Yiyu Shi;Jingtong Hu;Lei Yang;B. Nti - 通讯作者:
B. Nti
Toward Comprehensive Shifting Fault Tolerance for Domain-Wall Memories With PIETT
利用 PIETT 实现域壁存储器的全面移位容错
- DOI:
- 发表时间:
2023 - 期刊:
- 影响因子:3.7
- 作者:
S. Ollivier;Stephen Longofono;Prayash Dutta;Jingtong Hu;S. Bhanja;A. Jones - 通讯作者:
A. Jones
Stack-Size Sensitive On-Chip Memory Backup for Self-Powered Nonvolatile Processors
适用于自供电非易失性处理器的堆栈大小敏感片上内存备份
- DOI:
10.1109/tcad.2017.2666606 - 发表时间:
2017 - 期刊:
- 影响因子:2.9
- 作者:
Mengying Zhao;Chenchen Fu;Zewei Li;Qing'an Li;Mimi Xie;Yongpan Liu;Jingtong Hu;Zhiping Jia;Chun Jason Xue - 通讯作者:
Chun Jason Xue
Jingtong Hu的其他文献
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{{ truncateString('Jingtong Hu', 18)}}的其他基金
Collaborative Research: DESC: Type I: FLEX: Building Future-proof Learning-Enabled Cyber-Physical Systems with Cross-Layer Extensible and Adaptive Design
合作研究:DESC:类型 I:FLEX:通过跨层可扩展和自适应设计构建面向未来的、支持学习的网络物理系统
- 批准号:
2324937 - 财政年份:2024
- 资助金额:
$ 12.2万 - 项目类别:
Standard Grant
Collaborative Research: FuSe: R3AP: Retunable, Reconfigurable, Racetrack-Memory Acceleration Platform
合作研究:FuSe:R3AP:可重调、可重新配置、赛道内存加速平台
- 批准号:
2328972 - 财政年份:2024
- 资助金额:
$ 12.2万 - 项目类别:
Continuing Grant
Collaborative Research: FuSe: R3AP: Retunable, Reconfigurable, Racetrack-Memory Acceleration Platform
合作研究:FuSe:R3AP:可重调、可重新配置、赛道内存加速平台
- 批准号:
2328972 - 财政年份:2024
- 资助金额:
$ 12.2万 - 项目类别:
Continuing Grant
Collaborative Research: CNS Core:Small:IMPERIAL: In-Memory Processing Enhanced Racetrack Inspired by Accessing Laterally
协作研究:CNS Core:Small:IMPERIAL:受横向访问启发的内存处理增强赛道
- 批准号:
2133267 - 财政年份:2021
- 资助金额:
$ 12.2万 - 项目类别:
Standard Grant
Collaborative Research: CNS Core: Small: Towards Unsupervised Learning on Resource Constrained Edge Devices with Novel Statistical Contrastive Learning Scheme
合作研究:CNS 核心:小型:利用新颖的统计对比学习方案在资源受限的边缘设备上实现无监督学习
- 批准号:
2122320 - 财政年份:2021
- 资助金额:
$ 12.2万 - 项目类别:
Standard Grant
Collaborative Research:CNS Core: Small: Intermittent and Incremental Inference with Statistical Neural Network for Energy-Harvesting Powered Devices
合作研究:CNS 核心:小型:利用统计神经网络对能量收集供电设备进行间歇和增量推理
- 批准号:
2007274 - 财政年份:2020
- 资助金额:
$ 12.2万 - 项目类别:
Standard Grant
RAPID:Collaborative:Independent Component Analysis Inspired Statistical Neural Networks for 3D CT Scan Based Edge Screening of COVID-19
RAPID:协作:独立成分分析启发的统计神经网络,用于基于 3D CT 扫描的 COVID-19 边缘筛查
- 批准号:
2027546 - 财政年份:2020
- 资助金额:
$ 12.2万 - 项目类别:
Standard Grant
IRES Track I: International Research Experience for Students on Non-Volatile Processor Based Self-Powered Embedded Systems
IRES Track I:基于非易失性处理器的自供电嵌入式系统学生的国际研究经验
- 批准号:
1827009 - 财政年份:2018
- 资助金额:
$ 12.2万 - 项目类别:
Standard Grant
CRII: CSR: Enabling Efficient Non-Volatile Processors on Energy Harvesting Powered Embedded Systems
CRII:CSR:在能量收集供电的嵌入式系统上启用高效的非易失性处理器
- 批准号:
1830891 - 财政年份:2017
- 资助金额:
$ 12.2万 - 项目类别:
Standard Grant
CRII: CSR: Enabling Efficient Non-Volatile Processors on Energy Harvesting Powered Embedded Systems
CRII:CSR:在能量收集供电的嵌入式系统上启用高效的非易失性处理器
- 批准号:
1464429 - 财政年份:2015
- 资助金额:
$ 12.2万 - 项目类别:
Standard Grant
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