CIF:Small:High Performance Memories that Integrate Coding and Computer Architecture

CIF：Small：集成编码和计算机架构的高性能存储器

• 批准号: 1717602
• 负责人: Arthur Calderbank
• 金额: $ 47万
• 依托单位: Duke University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2017
• 资助国家: 美国
• 起止时间: 2017-09-01 至 2020-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1717602&HistoricalAwards=false
• 关键词: CIF; Small; Performance; Memories; Integrate

Part 1:Researchers continue to develope new memory and storage technologies for computer systems, including improvements to Flash memory in solid-state drives, as well as novel technologies that have not yet reached the market. These technologies offer new features---including greater storage density, or the ability to retain their data even without power---yet they also introduce new challenges, such as reduced lifetimes or the possibility that writing data into one part of the memory could disrupt values in other parts. Historically, imperfections in memory technologies have been overcome by encoding the information such that disrupted or lost data can be recovered. However, existing techniques do not suffice for the newly emerging memory technologies that have different imperfections and divergent usage models. This project is a collaboration between researchers in information theory (who study how to encode information for different purposes) and researchers in computer architecture (who study how to design computer systems, including memory and storage). The architects will identify exciting technologies and the problems they introduce, and the information theorists will develop new ways of encoding information to overcome these challenges. Whereas much research in coding is theoretical and lacks connection to the reality of computer systems, the collaboration with computer architects---who focus on implementation issues and costs---will ground the coding work and enhance its impact.To foster more interdisciplinary work in this research area, the research team will present half-day tutorials at conferences, including a coding tutorial at an architecture conference, and an architecture tutorial at an information theory conference. The investigators will continue to work with undergraduate research assistants, including students from an established summer outreach program at Duke?s Pratt School of Engineering. The investigators will also continue to recruit female research assistants alongside research assistants from under-represented populations; both investigators have extensive track records in this area and are committed to cultivating diversity in the computing research community.Part 2:The proposed research program seeks to improve the lifetime and fault tolerance of existing and emerging storage technologies---specifically Flash, 3D DRAM, and racetrack memory---by developing practical coding techniques that can be implemented in real-world systems. These storage technologies feature increased storage density, yet suffer the particular challenge of limited lifetime, that might otherwise limit their potential in microarchitectures.Historically, improvements in memory and storage have been due not only to advances in the memory technologies themselves, but also to innovations by computer architects who design memory and storage systems and by coding theorists who devise codes for data storage. The proposed research program is a collaboration between a coding theory group led by PI Calderbank and a computer architecture group led by co-PI Sorin. In their preliminary work, architecture problems have driven development of new theory, and advances in coding theory have driven development of new systems that can take advantage of them.The research thrusts can be classified by the memory technology, and all include specific challenges as well as more open-ended research directions: Specific objectives include1. Development of new coding solutions for racetrack memory that employ delimiter bits to identify single shift errors and practically implementable codes to correct the error, once identified. Introduction of coding across multiple racetracks (spatial diversity) to correct multiple shift errors.2. Development of virtual multilevel Flash cells that connect computer architecture with coding theoretic innovations, and evaluation of the tradeoff between host-visible capacity and lifetime.3. Development of new coding solutions that protect stacked DRAM designs from failures in bits, rows, banks, channels, dies and through silicon vias. Development of fundamental limits on how redundancy trades off against read/write latency, bandwidth requirements, and energy consumption in stacked designs.

第1部分：研究人员继续开发针对计算机系统的新内存和存储技术，包括改进固态驱动器的闪存以及尚未进入市场的新技术。 这些技术提供了新功能 - 包括更高的存储密度，或者即使没有电力也可以保留数据的能力 - 但它们也引入了新的挑战，例如降低的寿命或将数据写入内存的一部分可能会破坏其他部分的价值。从历史上看，记忆技术中的缺陷已经通过编码信息来克服，以便可以恢复中断或丢失的数据。 但是，现有技术对于具有不同缺陷和使用不同的使用模型的新出现的内存技术不足。 该项目是信息理论研究人员（研究如何出于不同目的编码信息）与计算机架构中的研究人员（研究如何设计计算机系统（包括内存和存储））之间的合作。 建筑师将确定激动人心的技术及其引入的问题，信息理论家将开发新的方法来克服这些挑战。 尽管编码方面的大量研究是理论上的，并且缺乏与计算机系统现实的联系，但与计算机架构师的合作 - - 他们专注于实施问题和成本 - 将基础编码工作并增强其影响。在该研究领域促进更多的跨学科工作，研究团队将在一个架构的架构中介绍一个半天的教程，包括在架构架构中进行编码的教程，并在架构架构中进行了架构，并将其培养。调查人员将继续与本科研究助理合作，其中包括杜克大学工程学院既定的夏季外展计划的学生。调查人员还将继续与代表性不足人群的研究助理一起招募女性研究助理；两位研究人员在这一领域都有广泛的记录，并致力于在计算研究社区中培养多样性。第2部分：拟议的研究计划旨在提高现有和新兴存储技术的寿命和容错性 - - 尤其是Flash，3D DRAM和赛马场 - 通过在现有系统中实现的实用编码技术。这些存储技术具有提高的存储密度，但终生有限的挑战可能会限制其在微构造中的潜力。从历史上讲，记忆和存储的改进不仅归因于记忆技术本身的进步，还归因于通过设计记忆和存储系统的计算机架构师的创新来设计记忆和存储系统的创新，并通过设计编码的理论家编码编码编码数据存储。拟议的研究计划是由Pi Calderbank领导的编码理论小组与Co-Pi Sorin领导的计算机架构组之间的合作。在他们的初步工作中，建筑问题推动了新理论的发展，编码理论的进步促使了可以利用它们的新系统的发展。研究推力可以通过内存技术进行分类，所有这些都包括具体的挑战以及更开放的研究方向：特定的目标包括1。开发针对赛马场内存的新编码解决方案，该解决方案采用定界符位来识别单个移位错误和实际上可实现的代码以纠正错误后。引入跨多个赛道（空间多样性）的编码以纠正多个偏移错误2。开发虚拟多级闪存单元，这些闪光单元将计算机架构与编码理论创新连接，并评估宿主可见能力和寿命之间的权衡。3。开发新的编码解决方案，以保护堆叠的DRAM设计免受碎屑，行，银行，频道，死亡以及通过硅VIA的故障。开发基本限制，即冗余如何抵抗读写潜伏期，带宽要求和堆叠设计中的能耗。

项目成果

GreenFlag: Protecting 3D-Racetrack Memory from Shift Errors

GreenFlag：保护 3D 赛道内存免受移位错误的影响

• DOI: 10.1109/dsn.2019.00016
• 发表时间: 2019
• 期刊: 49th IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2019
• 作者: Mappouras, Georgios;Vahid, Alireza;Calderbank, Robert;Sorin, Daniel J.
• 通讯作者: Sorin, Daniel J.

Topology-Aware Cooperative Data Protection in Blockchain-Based Decentralized Storage Networks

• DOI: 10.1109/isit44484.2020.9174443
• 发表时间: 2020-01
• 期刊: 2020 IEEE International Symposium on Information Theory (ISIT)
• 作者: Siyi Yang;Ahmed Hareedy;A. Calderbank;L. Dolecek

Increasing the Lifetime of Flash Memories Using Multi-Dimensional Graph-Based Codes

• DOI: 10.1109/itw44776.2019.8989395
• 发表时间: 2019-08
• 期刊: 2019 IEEE Information Theory Workshop (ITW)
• 作者: Ahmed Hareedy;Rohith Kuditipudi;Robert Calderbank

Extending Flash Lifetime in Embedded Processors by Expanding Analog Choice

• DOI: 10.1109/tcad.2018.2857059
• 发表时间: 2018-11-01
• 期刊: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
• 影响因子: 2.9
• 作者: Mappouras, Georgios;Vahid, Alireza;Sorin, Daniel J.
• 通讯作者: Sorin, Daniel J.

Foosball Coding: Correcting Shift Errors and Bit Flip Errors in 3D Racetrack Memory

桌上足球编码：纠正 3D 赛道内存中的移位错误和位翻转错误

• DOI: 10.1109/dsn48063.2020.00049
• 发表时间: 2020
• 期刊: 50th IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2020
• 作者: Archer, Samantha;Mappouras, Georgios;Calderbank, Robert;Sorin, Daniel
• 通讯作者: Sorin, Daniel