CRII: SHF: Improving Programmability of GPGPU/NVRAM Integrated Systems with Holistic Architectural Support

CRII：SHF：通过整体架构支持提高 GPGPU/NVRAM 集成系统的可编程性

• 批准号: 1657333
• 负责人: Xuehai Qian
• 金额: $ 17.5万
• 依托单位: University of Southern California
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2017
• 资助国家: 美国
• 起止时间: 2017-02-01 至 2020-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1657333&HistoricalAwards=false
• 关键词: CRII; SHF; Improving; Programmability; GPGPU

In the era of big data, the industry faces growing demand for higher computing power and large-capacity high performance storage. GPGPU and NVRAM are two prominent technologies that will play the key role in the "Big Data revolution". This project, which holistically improves the programmability of GPGPU/NVRAM integrated systems, tackles the "programmability bottleneck" faced in GPGPU and NVRAM. It will make it easier to develop correct applications in GPGPU and NVRAM with high performance. As a result, the project will enforce the desire of applying GPGPUs and NVRAM into a wide-range of HPC and big data applications which could then gain hundreds times speedup while ensuring recoverability. Overall, the outcomes of this project will help ensure the sustainable performance to support the supercomputing/big data processing in science and engineering (e.g. finance, medical, biology, petroleum, aerospace, and geology). This project will also contribute to society through engaging high-school and undergraduate students from minority-serving institutions into research, attracting women and under-represented groups into graduate education, expanding the computer engineering curriculum with GPGPU/NVRAM architectures, disseminating research infrastructure for education and training, and collaborating with the industry.This research investigates synergetic approaches and techniques to holistically improve the programmability of GPGPU/NVRAM integrated systems with the following techniques: (1) Timestamp-Based GPU Coherence Protocol. It avoids storage overhead by not storing sharing states (e.g. Shared, Modified, Exclusive, etc.) and the list of sharers. It reduces the traffic overhead by not sending explicit invalidation messages. (2) Integration of Persistency and the Scoped-Synchronization. This research aims to study the new notion of Persistent Scope (PS) , which incorporates the necessary persistency semantics into the existing scoped-synchronization in GPGPU programming models. Efficient architecture design that fully decouples consistency and persistency will be explored. (3) Data Sharing-Aware CTA Scheduler and Cache Management. This research plans to investigate a sharing-aware CTA scheduler that attempts to assign CTAs with data sharing to the same SM to improve temporal and spatial locality.

在大数据时代，该行业面临着对更高计算能力和大容量高性能存储的需求不断增长。 GPGPU和NVRAM是两种杰出的技术，它们将在“大数据革命”中起关键作用。该项目从整体上改善了GPGPU/NVRAM集成系统的可编程性，可以​​解决GPGPU和NVRAM中面临的“可编程性瓶颈”。这将使以高性能在GPGPU和NVRAM中开发正确的应用程序变得更加容易。结果，该项目将实施将GPGPU和NVRAM应用于大型HPC和大数据应用程序中的愿望，然后可以在确保可恢复性的同时获得数百倍的速度。总体而言，该项目的结果将有助于确保可持续绩效以支持科学和工程学中的超级计算/大数据处理（例如金融，医学，生物学，石油，航空航天和地质学）。该项目还将通过吸引来自少数派服务机构的高中生和本科生来为社会做出贡献GPGPU/NVRAM集成系统具有以下技术的可编程性：（1）基于时间戳的GPU相干协议。它通过不存储共享状态（例如共享，修改，独家等）和共享者列表来避免存储空间。它通过不发送明确的无效消息来减少开销的流量。 （2）持久性和范围同步的整合。这项研究旨在研究持久范围（PS）的新概念，该概念将必要的持久语义纳入GPGPU编程模型中现有的范围同步。 将探索充分破坏一致性和持久性的有效体系结构设计。 （3）数据共享感知的CTA调度程序和缓存管理。这项研究计划调查一种共享感知的CTA调度程序，该调度程序试图将具有数据共享的CTA分配给同一SM，以改善时间和空间位置。