High Performance Polar Decoders: Algorithm and Hardware Implementation

高性能 Polar 解码器：算法和硬件实现

• 批准号: 1509674
• 负责人: Zhiyuan Yan
• 金额: $ 30万
• 依托单位: Lehigh University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2015
• 资助国家: 美国
• 起止时间: 2015-08-01 至 2020-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1509674&HistoricalAwards=false
• 关键词: Performance; Polar; Decoders; Algorithm; Hardware

Error correction codes provide data reliability against possible errors, and hence are essential to all digital storage and communication systems. Polar codes, a recent breakthrough in the theory of error correction codes, are the first practical error correction codes that are asymptotically optimal in the sense of channel capacity. Their asymptotically optimal performance and low error floor make them promising candidates for future storage and communication systems. However, existing polar decoders suffer from inferior finite length error performance, long decoding delay, and inefficient hardware implementations. These issues form important obstacles to the adoption of polar codes in practice. Jointly addressing these interplaying challenges, the proposed research is a comprehensive investigation of polar decoders from the perspectives of error performance, complexity, delay, and hardware implementation, based on an integrated framework that harnesses the intricate relation between algorithms, their complexities and delays, and their hardware implementations.The proposed research aims to devise new polar decoders that not only achieve superior error performance but also have reduced delay, low complexities, and efficient hardware implementations. To this end, the objectives of the proposed research include: 1) New decoding algorithms for polar codes with improved performance and reduced complexity and delay; 2) Efficient architectures and hardware implementations of polar decoders; 3) Analytical, numerical and experimental performance evaluation of the proposed polar decoders, including a field-programmable gate array emulation platform. The proposed research tackles several key open research problems, such as error performance analysis of symbol-decision polar decoders, how to optimize the schedule of belief propagation decoding of polar codes, and belief propagation decoding of polar codes on over-complete factor graphs. The proposed research also will analytically characterize the error performance of symbol-decision polar decoders, thereby providing theoretical foundations for their future applications. The proposed field-programmable gate array emulation platform not only provides fast performance evaluation of proposed polar decoders, but also facilitates the selection of the appropriate values for various tradeoff parameters.The proposed research is transformative in both theory and practice. The proposed polar decoding algorithms as well as error performance analysis enrich the theory of error correction codes. The proposed decoders for polar codes will lead to better error performance, and have reduced decoding delay and efficient hardware implementations. These factors enable the adoption of polar codes to a wide variety of storage and communication systems, such as digital television, Ethernet, home networking, and Wi-Fi. The integrated design methodology, techniques, and results of the proposed research can be extrapolated to the implementation of other advanced algorithms, and hence impact a wide range of communication and signal processing systems. The integrated education program strengthens and diversifies the science and engineering workforce, and also bridges the gap between advanced signal processing algorithms and their efficient implementations, thus helping to maintain the nation's technological advantage.

错误校正代码可针对可能的错误提供数据可靠性，因此对于所有数字存储和通信系统至关重要。极地代码是误差校正理论的最新突破，是第一个实用的误差校正代码，在通道容量意义上是渐近最佳的。它们渐近的最佳性能和低误差地板使他们成为有希望的未来存储和通信系统的候选人。但是，现有的极地解码器患有较低的有限长度误差性能，长时间解码延迟以及效率低下的硬件实现。这些问题构成了在实践中采用极地法规的重要障碍。拟议的研究共同解决了这些相互作用的挑战，是从错误性能，复杂性，延迟和硬件实施的角度对极地解码器进行的全面调查，该框架基于一个集成的框架，该框架可以利用算法，复杂性和延误的算法之间的复杂性，其较低的综述性，而不仅可以使新的极性绩效延迟。有效的硬件实现。为此，拟议的研究的目标包括：1）针对极地代码的新解码算法，其性能提高，复杂性和延迟降低； 2）极地解码器的有效体系结构和硬件实现； 3）对拟议的极性解码器的分析，数值和实验性能评估，包括现场可编程的门阵列仿真平台。拟议的研究解决了几个关键的开放研究问题，例如符号 - 决策极性解码器的错误性能分析，如何优化极地代码的信念传播时间表，以及在过度完整因素图上对极地代码的信念传播解码。拟议的研究还将在分析上表征符号否定极性解码器的错误性能，从而为其未来应用提供理论基础。拟议的现场可编程的门阵列仿真平台不仅提供了对拟议的极性解码器的快速性能评估，而且还促进了为各种权衡参数选择适当值的选择。在理论和实践中，拟议的研究都是变革性的。提出的极性解码算法以及误差性能分析丰富了误差校正理论。拟议的极地代码解码器将导致更好的错误性能，并减少了解码延迟和有效的硬件实现。这些因素使得可以将极地代码采用到多种存储和通信系统，例如数字电视，以太网，家庭网络和Wi-Fi。拟议研究的综合设计方法，技术和结果可以推断到其他高级算法的实施中，因此会影响广泛的通信和信号处理系统。综合教育计划加强了科学和工程劳动力，还弥合了先进的信号处理算法与其有效实施之间的差距，从而有助于维持国家的技术优势。