SHF: Small: High Performance On-Chip Interconnects Design for Multicore Accelerators

SHF：小型：适用于多核加速器的高性能片上互连设计

• 批准号: 1423433
• 负责人: Eun Jung Kim
• 金额: $ 45万
• 依托单位: Texas A&M Engineering Experiment Station
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2014
• 资助国家: 美国
• 起止时间: 2014-07-15 至 2018-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1423433&HistoricalAwards=false
• 关键词: SHF; Small; Performance; Chip; Interconnects

Advances in technology have made it possible to accommodate an increasing number of transistors on a die, enabling Multicore Accelerators like Graphics Processing Units(GPUs) by integrating diverse components on a single chip. GPUs have recently gained attention as a cost-effective approach for data parallel architectures, and the fast scaling of the GPUs increases the importance of designing an ideal on-chip interconnection network, which significantly impacts the overall system performance.In this project, we propose to develop a framework for high-performance andenergy-efficient on-chip network mechanisms in synergy with Multicore Accelerator architectures. The desirable properties of a target on-chip network include re-usabilityacross a wide range of Multicore Accelerator architectures, maximization of the use ofrouting resources, and support for reliable and energy-efficient data transfer.This project will make significant advances in understanding the interplay between Multicore Accelerator and Network-on-Chip (NoC) architectures, which leads us toscalable solutions for performance, area and energy.While the major communication of Chip Multiprocessor (CMP) systems is core-to-corefor shared caches, major traffic of Multicore Accelerators is core-to-memory, which makes the memory controllers hot spots. Since Multicore Accelerators execute manythreads in order to hide memory latency, it is critical for the underlying NoC to provide high bandwidth.The key contributions expected from the project are: (1) building a simulation testbed and analyzing the behavior of on-chip traffic workloads in MulticoreAccelerators; (2) proposing mechanisms for a high-performance and energy-efficient NoC by utilizing emerging memory and NoC technologies in addition to novel topologiesand routing mechanisms; (3) developing methodologies at the NoC level that will support data prefetching mechanisms in the Multicore Accelerators; and (4) providingmulticast support and packet coalescing in the on-chip network to guarantee bettersystem throughput. The results from this project are likely to foster new research directions in severalareas of Computer Architecture and Parallel Computing. Also, high-performance and energy-aware computing and communication research is applicable to other areas,such as Embedded Systems and Cloud Computing. We will develop web-based tutorials to present and disseminate the results of this project, including tools and techniques, to a broad audience.

技术的进步使得可以在模具上容纳越来越多的晶体管，从而使多核心加速器（例如图形处理单元（GPU）（GPU））通过单个芯片上的多种组件进行整合。最近，GPU作为数据并行架构的一种具有成本效益的方法而引起关注，GPU的快速扩展增加了设计理想的芯片片段互连网络的重要性，这显着影响了整个系统性能。在此项目中，我们建议在跨架构机构中开发高实验性和Enerenergy-Chartery网络的框架。目标芯片网络的理想特性包括重新限制多种多项加速器体系结构，最大化使用资源的使用以及支持可靠和能节能的数据传输的支持。该项目将在理解多项式加速器和网络上的范围（Noc-Chip and-Chip）架构上的多项式加速器和网络之间的相互作用方面取得重大进展芯片多处理器（CMP）系统的主要通信是共享库的核心对核心，多核算加速器的主要流量是核心到序列，这使内存控制器热点热点。由于多核算加速器执行许多线程以隐藏内存延迟，因此提供高带宽的基础NOC至关重要。项目预期的关键贡献是：（1）构建模拟测试台并分析多核酸酯中芯片交通工作负载的行为； （2）除了新的拓扑结构和路由机制外，还利用新兴记忆和NOC技术提出了高性能和节能NOC的机制； （3）在NOC级别开发方法，该方法将支持多核算加速器中的数据预取机制； （4）在片上网络中提供大型支持和数据包合并，以确保更好的系统吞吐量。该项目的结果可能会在计算机架构和并行计算的多个研究中促进新的研究方向。同样，高性能和能源感知计算和通信研究适用于其他领域，例如嵌入式系统和云计算。我们将开发基于Web的教程，以向广泛的受众介绍和传播该项目的结果，包括工具和技术。