SHF: Small: Collaborative Research: Exploring Energy-Efficient GPGPUs Through Emerging Technology Integration

SHF：小型：协作研究：通过新兴技术集成探索节能 GPGPU

• 批准号: 1320100
• 负责人: Renato Figueiredo
• 金额: $ 24.37万
• 依托单位: University of Florida
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2013
• 资助国家: 美国
• 起止时间: 2013-08-01 至 2018-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1320100&HistoricalAwards=false
• 关键词: SHF; Small; Collaborative; Research; Exploring

Nowadays, graphics processing units (GPUs) have been widely adopted for general-purpose computing, and are known as GPGPUs. However, current and future GPGPUs confront power and energy as the dominant constraints. The number of transistors integrated on a single GPU chip continues to increase due to shrinking feature size and the demand for massively parallel computing cores to increase throughput. On the other hand, the continuous decrease of transistor supply voltage at each new technology node has largely stalled because of leakage constraints, leading to an ever-increasing power density. Therefore, future GPGPUs must become more inherently energy efficient to avoid hitting the power wall. To meet the increasing demands on performance and energy-efficiency, emerging technologies such as non-volatile memory, inter-bank tunneling field effect transistors (TFETs), silicon nanophotonics, and three-dimensional (3D) integration are being deployed in hardware design and promise realization of power efficiency at a scale never expected before. The investigators are exploring a synergetic program to holistically and hierarchically improve the GPGPU's energy efficiency through emerging technology integration. The project objectives include (1) non-volatile memory in the GPU computing cores and low-power mechanisms to substantially reduce leakage and dynamic power consumption; (2) a hybrid TFET-CMOS (complementary metal-oxide semiconductor) methodology to effectively address the energy challenge at both intra- and inter-core levels; (3) a novel 3D-stacked throughput architecture based on silicon-nanophotonics technology to improve memory access performance yet reduce power consumption; (4) integration of the key research innovations and cross-technology optimizations to fully explore the potential of GPGPU design enabled by these emerging technologies. The proposed research will facilitate GPGPUs staying on track with deep sub-micron scaling and meeting the increasing demand for high-performance computing, and will hence benefit numerous real-life applications. This project will also contribute to society through engaging high-school and undergraduate students from minority-serving institutions in research, attracting women and other under-represented groups into graduate education, expanding the computer engineering curriculum with GPGPU power modeling and optimization techniques, disseminating research infrastructure for education and training, and collaborating with the GPU R&D industry.

如今，图形处理单元（GPU）已广泛用于通用计算，被称为GPGPU。然而，当前和未来的 GPGPU 面临着功率和能源的主要限制。由于特征尺寸的缩小以及对大规模并行计算核心提高吞吐量的需求，单个 GPU 芯片上集成的晶体管数量持续增加。另一方面，由于漏电限制，每个新技术节点晶体管电源电压的持续降低已基本停止，导致功率密度不断增加。因此，未来的 GPGPU 必须变得更加节能，以避免撞上电源墙。为了满足对性能和能效日益增长的需求，非易失性存储器、组间隧道场效应晶体管 (TFET)、硅纳米光子学和三维 (3D) 集成等新兴技术正在硬件设计和应用中得到部署。承诺以前所未有的规模实现能源效率。研究人员正在探索一项协同计划，通过新兴技术集成来全面、分层地提高 GPGPU 的能源效率。该项目的目标包括（1）GPU计算核心中的非易失性存储器和低功耗机制，以大幅减少泄漏和动态功耗； (2) 混合 TFET-CMOS（互补金属氧化物半导体）方法，可有效解决内核内和内核间的能源挑战； (3) 基于硅纳米光子技术的新型 3D 堆叠吞吐量架构，可提高内存访问性能并降低功耗； （4）整合关键研究创新和跨技术优化，充分挖掘这些新兴技术所赋能的GPGPU设计潜力。拟议的研究将有助于 GPGPU 保持在深亚微米尺度的轨道上，并满足对高性能计算日益增长的需求，从而使众多实际应用受益。该项目还将通过吸引少数民族服务机构的高中生和本科生参与研究、吸引女性和其他弱势群体进入研究生教育、利用 GPGPU 功率建模和优化技术扩展计算机工程课程、传播研究成果等方式为社会做出贡献。教育和培训基础设施，以及与GPU研发行业的合作。