Lifetime Reliability of Systems-on-Chip: Unified Modeling and Dynamic Reliability Management

片上系统的寿命可靠性：统一建模和动态可靠性管理

• 批准号: 1263438
• 负责人: Cristinel Ababei
• 金额: $ 17.33万
• 依托单位: SUNY at Buffalo
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2012
• 资助国家: 美国
• 起止时间: 2012-08-16 至 2013-11-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1263438&HistoricalAwards=false
• 关键词: Lifetime; Reliability; Systems; Chip; Unified

Future integrated circuits will contain tens, hundreds, or even thousand cores per chip. However, technology downscaling that can make this possible may also make the underlying hardware less reliable due to an increasing number of defects and wear out mechanisms. Therefore, one of the major problems facing the design of multiprocessor systems-on-chip is reliability. Because either the cores or the network-on-chip (used for communication between the cores) can become a reliability bottleneck for these systems, it is imperative that the reliability be addressed in a unified manner. To address the reliability challenge, this research develops a novel unified theoretical lifetime reliability modeling framework. This framework is based on efficient Monte Carlo methods to treat multiprocessor systems-on-chip as a combination of computation and communication units. The goal of this research is to develop new dynamic reliability management techniques based on dynamic voltage and frequency scaling and application remapping. Based on control theory concepts, these techniques proactively improve the lifetime reliability of multicore systems.The proposed dynamic reliability management techniques enable the development of more reliable multiprocessor systems-on-chip, which have a dramatic impact on society via applications ranging from entertainment and gaming to bio-engineering, military and space. More broadly, the results of this project impact significantly the design of future integrated systems by advancing the understanding of the tradeoffs between reliability as a new design concern and power consumption, performance and area as traditional objectives.

未来的集成电路将包含每个芯片数十万，数百甚至千的内核。但是，由于越来越多的缺陷和磨损机制，技术降低的降低可能使基础硬件的可靠性降低。因此，片上多处理器系统的设计面临的主要问题之一是可靠性。由于芯片上的核心或网络（用于核心之间的通信）可以成为这些系统的可靠性瓶颈，因此必须以统一的方式解决可靠性。为了应对可靠性挑战，本研究开发了一种新颖的统一理论寿命可靠性建模框架。该框架基于有效的蒙特卡洛方法，可将芯片上的多处理器系统作为计算和通信单元的组合。这项研究的目的是基于动态电压，频率缩放和应用程序重新映射开发新的动态可靠性管理技术。基于控制理论概念，这些技术主动提高了多核心系统的寿命可靠性。拟议的动态可靠性管理技术使得可以开发更可靠的多处理器系统中的多处理器系统，从而通过娱乐和游戏到生物工程，军事，军事和空间，对社会产生巨大影响，这些应用程序对社会产生了巨大影响。更广泛地说，该项目的结果通过促进对可靠性作为新的设计关注和功耗，绩效和领域作为传统目标之间的权衡的理解，从而对未来集成系统的设计产生了重大影响。