Cross-Layer Fault Resilience for Interconnection Networks in Multi-core SoCs

多核 SoC 中互连网络的跨层故障恢复

• 批准号: 1252500
• 负责人: Sudeep Pasricha
• 金额: $ 18万
• 依托单位: Colorado State University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2013
• 资助国家: 美国
• 起止时间: 2013-04-01 至 2017-03-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1252500&HistoricalAwards=false
• 关键词: Cross; Layer; Fault; Resilience; Interconnection

Shrinking fabrication feature sizes and the increasing proliferation of mixed-signal and 3D integration are elevating rates of faults, variation, and aging related degradation in electronic integrated circuits, threatening the reliability of communication between processing cores in system-on-chip (SoC) architectures. The goal of this project is to realize system-level computer-aided design (CAD) automation techniques and tools to assist chip designers to trade off reliability with competing design constraints for on-chip interconnection networks within tight time-to-market constraints. This novel framework will exploit cross-layer insights about the software application, hardware intellectual property blocks, and circuits, as well as knowledge of key factors impacting susceptibility to runtime faults for network routers and interfaces. By achieving reliability goals and multi-objective design trade-offs for on-chip interconnection network fabrics with orders of magnitude lower time complexity and overhead than is possible today, this project will transform the design of multi-core SoCs that already permeate most facets of our daily lives. The research will drive a tightly integrated education plan to inspire K-12 students toward STEM careers, ensure workforce continuity, and increase participation of veterans, undergraduates, and women via capstone projects and distance education initiatives. A new course on fault tolerant chip design will be created and existing courses on computer architecture and embedded systems will be enhanced with reliability-centric components. By exposing graduate students to diverse aspects of CAD algorithms, SoC architectures, and parallel applications, the educational component of this project will contribute to an agile high-tech workforce that will maintain continued US leadership in technological innovation.

缩小的制造特征大小以及混合信号和3D整合的增殖增加是电子整合电路中故障，变化和相关降解的速率的提高，威胁到系统 - 芯片（SOC）体系结构中处理核心之间通信的可靠性。该项目的目的是实现系统级计算机辅助设计（CAD）自动化技术和工具，以帮助芯片设计人员在紧密的市场限制内遇到芯片互连网络的竞争设计约束，以交易可靠性。这个新颖的框架将利用有关软件应用程序，硬件知识属性块和电路的跨层洞察力，以及有关影响网络路由器和接口的运行时故障敏感性的关键因素的知识。通过实现片上互连网络面料的可靠性目标和多目标设计权衡，其时间级要比今天的复杂性低，并且比今天可能的较低，这将改变已经渗透到我们日常生活中大多数方面的多核SOC的设计。这项研究将推动一项紧密融合的教育计划，以通过Capstone项目和远程教育计划来激发K-12学生迈向STEM职业，确保劳动力连续性以及增加退伍军人，本科生和妇女的参与。将创建有关容忍芯片设计的新课程，并通过以可靠性为中心的组件来增强计算机架构和嵌入式系统的现有课程。通过使研究生了解CAD算法，SOC架构和并行应用的各个方面，该项目的教育组成部分将有助于敏捷的高科技劳动力，该劳动力将保持美国在技术创新方面的持续领导。