TWC: Phase: Medium: Collaborative Proposal: Understanding and Exploiting Parallelism in Deep Packet Inspection on Concurrent Architectures

TWC：阶段：中：协作提案：理解和利用并发架构深度数据包检查中的并行性

• 批准号: 1228782
• 负责人: Somesh Jha
• 金额: $ 95.08万
• 依托单位: University of Wisconsin-Madison
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2012
• 资助国家: 美国
• 起止时间: 2012-09-01 至 2018-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1228782&HistoricalAwards=false
• 关键词: TWC; Phase; Medium; Collaborative; Proposal; TWC; Phase; Medium; Collaborative; Proposal

Deep packet inspection (DPI) is a crucial tool for protecting networks from emerging and sophisticated attacks. However, it is becoming increasingly difficult to implement DPI effectively due to the rising need for more complex analysis, combined with the relentless growth in the volume of network traffic that these systems must inspect. To address this challenge, future DPI technologies must exploit the power of emerging highly concurrent multi- and many-core platforms. Unfortunately, however, current DPI systems severely limit their use of parallelism by either resorting to coarse-grained load-balancing or restricting their analysis to very simple, hard-coded detectors.In order to fully exploit parallel hardware platforms, in this project we develop a comprehensive approach that introduces parallelism across all stages of the complex DPI pipeline. We investigate application-independent scheduling strategies that take existing DPI analyses and automatically parallelize their processing. We do so by mapping them into a domain-specific intermediary representation that abstracts from specifics of the underlying hardware architecture while providing low-level consistency guarantees. Conceptually, the project's goal is to virtualize and abstract parallelism as a fundamental primitive, just like how virtual memory abstracts away physical memory size limitations from programmers.

深度数据包检查（DPI）是保护网络免受新兴和复杂攻击的关键工具。但是，由于对更复杂的分析的需求不断增加，加上这些系统必须检查的网络流量量的不断增长，因此有效实施DPI变得越来越困难。 为了应对这一挑战，未来的DPI技术必须利用出现高度并发的多核平台的力量。但是，不幸的是，当前的DPI系统通过诉诸粗粒载荷平衡或将其分析限制为非常简单的，硬编码的探测器来严重限制了对并行性的使用。在这个项目中，我们开发了一种全面的方法，可以在该项目中完全利用并行的方法，从而在复杂的DPI Pipeline的所有阶段中介绍了平行级别。我们研究了与应用程序无关的调度策略，以进行现有的DPI分析并自动使其处理。我们这样做是通过将它们映射到特定领域的中间表示形式中，该表示从基础硬件体系结构的细节中抽象出，同时提供低级的一致性保证。从概念上讲，项目的目标是虚拟和抽象的并行性作为基本原始性，就像虚拟内存如何从程序员中抽象物理内存大小的限制一样。