SHF: Medium: Intelligent and Efficient Data Movement for Multicore Systems

SHF：中：多核系统的智能且高效的数据移动

• 批准号: 0964106
• 负责人: Marinus Kaashoek
• 金额: $ 108万
• 依托单位: Massachusetts Institute of Technology
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2010
• 资助国家: 美国
• 起止时间: 2010-06-01 至 2015-05-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0964106&HistoricalAwards=false
• 关键词: SHF; Medium; Intelligent; Efficient; Data

Multicore chips with hundreds of cores will likely be available soon. Current trends suggest that cores will be relatively simple, that on-chip memory will be partitioned into per-core caches, and that each cache will be relatively small. Furthermore, chips will continue to be pin-limited and therefore DRAM bandwidth won't scale with the number of cores.Parallel software that is data intensive has the potential to run well on multicore processors due to the large total amount of on-chip cache, but requires effective use of the distributed on-chip caches. The dangers are that data used by many cores will be duplicated in many cores' caches, decreasing the total amount of distinct data that can be cached; and that some cores may incur DRAM loads trying to access more data than fits in their caches, while other cores have spare cache space.As the number of cores per DRAM interface and the latencies between caches on a chip increase, it is important for software to manage the distributed caches well. A collaborative approach that involves architects and systems researchers to extend the memory interface to provide control over data placement and enable on-chip efficient data movement provides a holistic solution. Specifically, this work proposes data-movement control (DMC) interface, which includes support for cache-to-cache transfers, batching of several cache lines, sending a message to a core that is close to a cache that holds a particular data item, and data monitoring. The proposal also includes techniques to route data over the interconnect that will provide high performance for the DMC interface.If successful, DMC will help data-intensive applications avoid memory bottlenecks and allow them to run well on future multicore processors. A full-system simulator will allow other researchers to explore intelligent and efficient data management and enable research projects in MIT's graduate computer architecture class, educating students about the challenges of multicore computing.

具有数百个核心的多核芯片可能很快就会面世。目前的趋势表明，内核将相对简单，片上内存将被划分为每个内核的缓存，并且每个缓存将相对较小。此外，芯片将继续受到引脚限制，因此 DRAM 带宽不会随着内核数量的增加而扩展。由于片上缓存总量较大，数据密集型并行软件有可能在多核处理器上良好运行，但需要有效利用分布式片上缓存。危险在于，许多核心使用的数据将在许多核心的缓存中重复，从而减少可缓存的不同数据的总量；并且某些核心可能会产生 DRAM 负载，试图访问超出其缓存容量的数据，而其他核心则有备用缓存空间。随着每个 DRAM 接口的核心数量以及芯片上缓存之间的延迟的增加，这对于软件来说非常重要很好地管理分布式缓存。 架构师和系统研究人员合作扩展内存接口以控制数据放置并实现片上高效数据移动，从而提供了整体解决方案。 具体来说，这项工作提出了数据移动控制（DMC）接口，其中包括对缓存到缓存传输的支持、对多个缓存行的批处理、向靠近保存特定数据项的缓存的核心发送消息，和数据监控。 该提案还包括通过互连路由数据的技术，这将为DMC接口提供高性能。如果成功，DMC将帮助数据密集型应用程序避免内存瓶颈，并使它们能够在未来的多核处理器上良好运行。 全系统模拟器将允许其他研究人员探索智能和高效的数据管理，并支持麻省理工学院研究生计算机架构课程的研究项目，教育学生了解多核计算的挑战。