II-EN: Infrastructure Acquisition for Statistical Power, Leakage, and Timing Modeling Towards Realization of Robust Complex Nanoelectronic Circuits

II-EN：统计功率、泄漏和时序建模的基础设施采集，以实现鲁棒的复杂纳米电子电路

• 批准号: 0854182
• 负责人: Saraju Mohanty
• 金额: $ 24.93万
• 依托单位: University of North Texas
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2009
• 资助国家: 美国
• 起止时间: 2009-08-01 至 2012-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0854182&HistoricalAwards=false
• 关键词: II; EN; Infrastructure; Acquisition; Statistical

This award is funded under the American Recovery and Reinvestment Act of 2009 (Public Law 111-5).Accurate modeling of power, leakage, and timing while accounting for process variations, is crucial for the manufacturable design of nanoscale CMOS integrated circuits. Thus, there is a pressing need for statistical models that allow design engineers to make fast architectural or system level design space exploration without resorting to a complete design iteration, from system to physical level. The thrust of the project's methodology is the progression of data transfer from lowest (transistor) to highest (system) level while utilizing minimal data from actual silicon. This allows for fast concurrent design for manufacturing of new systems with a clear delineation of the needed data at every level.To conduct research on nanoscale CMOS modeling that can be used for realization of robust circuits, and to make the deliverables available to the VLSI and educational communities, the project utilizes the following infrastructure: (1) Specialized equipment: mixed-signal analyzer, probing station and arbitrary waveform generator for sample data collection, probing and analysis for model validation.(2) Computing resources: a high-end, 4 processor server with 16-GB local memory and 4-TB RAID5 storage to be used by two faculty members and 10 students for nanoscale data acquisition, control, analysis, and storage.(3) Research and development personnel to develop the models and libraries, to validate the methodology, and to maintain the infrastructure.The educational impact of the project is 3-fold: impact on curricula at UNT, impact on curricula of other researchers who will use this infrastructure, and impact on the community colleges around the Dallas-Fort Worth metroplex.

该奖项根据 2009 年美国复苏和再投资法案（公法 111-5）提供资金。在考虑工艺变化的同时对功率、泄漏和时序进行精确建模对于纳米级 CMOS 集成电路的可制造设计至关重要。因此，迫切需要统计模型，使设计工程师能够快速进行架构或系统级设计空间探索，而无需诉诸从系统到物理级别的完整设计迭代。该项目方法的主旨是在利用实际芯片中最少的数据的同时，从最低（晶体管）级别到最高（系统）级别进行数据传输。这允许快速并发设计新系统的制造，并清楚地描述每个级别所需的数据。对可用于实现鲁棒电路的纳米级 CMOS 建模进行研究，并使可交付成果可供 VLSI 和教育社区，该项目利用以下基础设施：（1）专用设备：混合信号分析仪、探测站和任意波形发生器，用于样本数据收集、探测和分析以进行模型验证。（2）计算资源：高端、 4 处理器服务器具有16GB本地内存和4TB RAID5存储，供两名教员和10名学生使用，用于纳米级数据采集、控制、分析和存储。（3）研发人员开发模型和库，进行验证该项目的教育影响有三方面：对 UNT 课程的影响、对将使用该基础设施的其他研究人员的课程的影响以及对达拉斯堡周围社区大学的影响值得大都会。