GOALI (Industry-University Collaborative Project): Collaborative Research: Scalable Techniques for Detecting Small-Delay Defects in Nanometer Integrated Circuits

GOALI（产学合作项目）：合作研究：检测纳米集成电路中小延迟缺陷的可扩展技术

• 批准号: 0823992
• 负责人: Mark Tehranipoor
• 金额: $ 16.47万
• 依托单位: University of Connecticut
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2008
• 资助国家: 美国
• 起止时间: 2008-09-01 至 2012-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0823992&HistoricalAwards=false
• 关键词: GOALI; Industry; University; Collaborative; Project

ObjectiveThe objective of this project is to develop new test techniques that target small-delay defects in nanoscale integrated circuits. The approach is based on the use of the output-deviations measure as a surrogate "long-path" coverage metric for small-delay defects. The project will be carried out in partnership with AMD Corporation and other industrial collaborators. Intellectual Merit: Small-delay defects, induced by process variations, crosstalk, power-supply noise, and resistive opens/shorts, etc., are major quality and reliability concerns in the semiconductor industry. Current industry practices are not only inadequate for small-delay defects, but test costs are skyrocketing as well (estimated to be more than 50% of manufacturing cost). This project is focused on test generation using scalable methods that can provide comprehensive defect screening for industrial circuits. It includes the following components: (i) a gate-delay-defect probability measure to model delay faults; (ii) use of gate-delay-defect probabilities for computing output deviations; (iii) layout-aware, deviation-based test-pattern selection/generation for high defect coverage.Broader Impacts: This project will lead to higher shipped-product quality, increased in-field reliability, and reduced test cost. Benefits for society include reliable electronics for healthcare, cheaper and dependable computing platforms for servers, weather forecasting, financial transactions, and more, and realization of the much sought-after zero-defects for automotive applications. Students will be trained for the workforce through research experience, coursework, and relevant industry internships. A concerted effort will be made to involve under-represented groups, for example through the Semiconductor Research Corporation fellowship programs. Tutorials will be presented and special sessions will be organized at major conferences.

目标该项目的目标是开发针对纳米级集成电路中小延迟缺陷的新测试技术。 该方法基于使用输出偏差测量作为小延迟缺陷的替代“长路径”覆盖度量。 该项目将与 AMD 公司和其他工业合作伙伴合作开展。智力优点：由工艺变化、串扰、电源噪声和电阻开路/短路等引起的小延迟缺陷是半导体行业的主要质量和可靠性问题。 目前的行业实践不仅不足以应对小延迟缺陷，而且测试成本也飞涨（估计超过制造成本的 50%）。 该项目专注于使用可扩展方法进行测试生成，为工业电路提供全面的缺陷筛选。 它包括以下部分： (i) 门延迟缺陷概率测量，用于对延迟故障进行建模； (ii) 使用栅极延迟缺陷概率来计算输出偏差； (iii) 布局感知、基于偏差的测试模式选择/生成，以实现高缺陷覆盖率。更广泛的影响：该项目将提高出货产品质量、提高现场可靠性并降低测试成本。 为社会带来的好处包括用于医疗保健的可靠电子产品、用于服务器、天气预报、金融交易等的更便宜且可靠的计算平台，以及实现备受追捧的汽车应用零缺陷。学生将通过研究经验、课程作业和相关行业实习接受劳动力培训。我们将共同努力让代表性不足的群体参与其中，例如通过半导体研究公司奖学金计划。 将在主要会议上提供教程并组织特别会议。