CPA-DA: Integrated Methodology for Managing Noise in Next Generation Multi-Core SoCs

CPA-DA：下一代多核 SoC 中噪声管理的集成方法

• 批准号: 0811317
• 负责人: Eby Friedman
• 金额: $ 24.89万
• 依托单位: University of Rochester
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2008
• 资助国家: 美国
• 起止时间: 2008-08-01 至 2012-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0811317&HistoricalAwards=false
• 关键词: CPA; DA; Integrated; Methodology; Managing

CPA-DA: Integrated Methodology for Managing Noise in Next Generation Multi-Core SoCsProposal No. 0811317PI: Eby G. FriedmanUniversity of RochesterAbstractThe focus of this project is the development of an integrated methodology for managing noise that addresses the multiple interactions among different noise sources to support the design of next generation multi-core mixed-signal systems-on-chips (SoCs). Accurate, yet computationally efficient noise models will be developed and combined with noise reduction techniques to effectively control the signal characteristics within a system. Leveraging the classical noise propagation model from communications, a novel unified approach will be applied to model noise generation, propagation, and reception among diverse system components, supporting the development of aggregate noise cancellation techniques. Design tradeoffs to alleviate the effects of multiple noise sources will be investigated and design guidelines will be developed. The interdependence among diverse noise effects at the device, circuit, and multi-core levels will be investigated and design strategies that minimize noise across mixed-signal components will be developed. Emphasis will be placed on the global features responsible for generating and propagating noise among different system components, such as the power distribution networks, the global interconnect lines, the inter-core synchronization schemes, and the silicon substrate. The sensitivity of the noise models and reduction techniques to process and environmental variations will also be investigated. The ultimate objective is that upon completion of this project, signal uncertainty in analog circuits and delay uncertainty in digital circuits due to multiple noise effects in multi-core SoCs will be better understood and accurately modeled in a computationally efficient manner, while integrated noise reduction methodologies will be developed to design the next generation of high complexity, high performance integrated circuits. These research results will provide new directions for educational initiatives targeting both university teaching and research activities in the broader academic community. Undergraduate projects demonstrating the practical aspects of the research results will be devised in collaboration with graduate students. A course related to the research will be developed and offered to graduate and senior undergraduate students with disparate backgrounds. A tutorial will be prepared for presentation at major conferences. The PI will also participate in a University program intended to enhance minority enrollment in graduate engineering and science programs. The intellectual and social objectives of this project are intended to greatly surpass existing limitations in the system-on-chip design process, enabling the development of future generations of multi-core, mixed-signal SoCs, while contributing towards the advancement and diversity of the science and engineering workforce.

CPA-DA: Integrated Methodology for Managing Noise in Next Generation Multi-Core SoCsProposal No. 0811317PI: Eby G. FriedmanUniversity of RochesterAbstractThe focus of this project is the development of an integrated methodology for managing noise that addresses the multiple interactions among different noise sources to support the design of next generation multi-core mixed-signal systems-on-chips (SoCs).将开发准确但具有计算高效的噪声模型，并与降低降噪技术结合使用，以有效地控制系统内的信号特性。利用通信的经典噪声传播模型，一种新型的统一方法将应用于不同系统组件之间的噪声，传播和接收模型，以支持骨料消除技术的发展。将研究以减轻多种噪声源的影响的设计权衡，并将制定设计指南。将研究设备，电路和多核水平的各种噪声效应之间的相互依赖性，并设计策略，以最大程度地减少混合信号组件的噪声。重点将放在负责在不同系统组件之间产生和传播噪声的全局特征，例如功率分配网络，全局互连线，核心间同步方案和硅基板。还将研究噪声模型和还原技术对过程和环境变化的敏感性。最终目标是，在完成该项目后，模拟电路的信号不确定性以及由于多核SOC中多个噪声效应而导致的数字电路的延迟不确定性将得到更好的理解，并且以计算上有效的方式进行了准确的建模，而集成的降噪方法将开发出来，以设计下一代的高复杂性，高表现性能，高表现性能，高表现循环。这些研究结果将为针对更广泛学术界的大学教学和研究活动的教育计划提供新的方向。展示研究结果的实际方面的本科项目将与研究生合作设计。将开发与研究有关的课程，并为具有不同背景的研究生和高级本科生提供。将准备一个教程在主要会议上演讲。 PI还将参加一项旨在提高研究生工程和科学课程的少数群体入学率的大学课程。该项目的智力和社会目标旨在极大地超过芯片设计过程中的现有局限性，从而使后代的多核，混合信号SOC的发展发展，同时为科学和工程劳动力的发展和多样性做出了贡献。