CPA: Collaborative Research: Formal Techniques for Designing Globally Asynchronous and Locally Synchronous Systems (FMGALS)

CPA：协作研究：设计全局异步和局部同步系统（FMGALS）的形式技术

• 批准号: 0702539
• 负责人: Kenneth Stevens
• 金额: $ 20万
• 依托单位: University of Utah
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2007
• 资助国家: 美国
• 起止时间: 2007-07-01 至 2010-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0702539&HistoricalAwards=false
• 关键词: CPA; Collaborative; Research; Formal; Techniques

Collaborative Proposal ID(s): 0702316 and 0702539Title:: Collaborative Research: Formal Techniques for Designing Globally Asynchronous and Locally Synchronous Systems (FMGALS)PIs: Sandeep K. Shukla (Virginia Tech) & Kenneth Stevens (University of Utah)The increased momentum towards Globally Asynchronous and Locally Synchronous(GALS) design has been necessitated by three factors. First, due to decreasing feature size of CMOS technology, and increasing clock frequency in the gigahertz range, the clock period is diminishing towards a limit where efficient synchronous clocking throughout the chip is getting difficult. Second, IP reuse based System on Chip (SoC) design becomes easier if all IPs do not have to be optimized for the same clocking scheme, and finally, increasing power consumption in clock buffers, global repeaters and clock tree is a growing industrial concern.However, correctly designing GALS systems is error prone and difficult.Asynchronous design tools and methodologies are almost nonexistent outside academia with a few exceptions. Research towards tools and methodologies for GALS design is imperative. Given the subtlety and complexity of these problems, we believe that grounding any GALS methodology in formal methods is important and necessary. Real implementation of protocols into on-chip fabrics and experimental validation of the efficacy of such designs is necessary for the wide acceptance of the design methodologies.In this project, the Virginia Polytechnic and State University and the University of Utah teams will collaborate to develop a formal basis for designing and experimenting with the trade-offs of various GALS solutions, and actually fabricate such solutions on-chip to calibrate the solutions.Other than the research and educational impact of inventing new GALS techniques, and methodologies for formally capturing the protocols and verifying them, the broader impact of this project will constitute collaborative team work and training of students to work in a distributed development environment, inclusion of undergraduate researchers into research, and special effort of including minority students into the project.

协作提议ID：0702316和0702539TITLE ::协作研究：设计用于设计全球异步和本地同步系统（FMGALS）的形式技术PIS：Sandeep K. Sandeep K. Shukla（Virginia Tech）（Virginia Tech）和肯尼斯·史蒂夫斯（Utimals），与犹他州的同步（UTIMEN）同步（尤其是犹他州）的同步（已经有三个因素需要。首先，由于CMOS技术的特征大小和Gigahertz范围内的时钟频率的增加，时钟周期正在降低，因为整个芯片中有效的同步时钟都变得越来越困难。其次，如果所有IP都不必针对同一时钟方案进行优化，那么基于芯片（SOC）设计的基于IP重复使用的系统就变得更加容易，最后，增加时钟缓冲，全球折扣和时钟树的功耗增加是一个日益增长的工业问题。对GALS设计的工具和方法的研究是必须的。鉴于这些问题的微妙和复杂性，我们认为以形式方法将所有GALS方法基础是重要且必要的。 真正实施协议中的芯片织物和此类设计功效的实验验证对于广泛接受设计方法是必要的。在该项目中，弗吉尼亚理工学院和州立大学和犹他州大学将合作开发正式的基础，以实现设计和实验性的研究和实验性研究。发明新的GALS技术以及用于正式捕获协议并验证它们的方法论，该项目的更广泛影响将构成合作团队的工作和对学生进行分布式发展环境中的工作，将本科研究人员纳入研究中，以及将少数派学生纳入该项目的特殊努力。