Self-Adjusting Architectures/Circuits for Improved Performance and Reduced Design Complexity

自调节架构/电路可提高性能并降低设计复杂性

• 批准号: 0541337
• 负责人: Gokhan Memik
• 金额: $ 45万
• 依托单位: Northwestern University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2006
• 资助国家: 美国
• 起止时间: 2006-05-01 至 2009-04-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0541337&HistoricalAwards=false
• 关键词: Self; Adjusting; Architectures; Circuits; Improved

Recent trends of nanoscale integrated circuits will not be mitigated by contemporary architectural innovations and will introduce significant bottlenecks in the design of future microprocessors. First, the growing complexity of models for high performance circuits make it difficult to identify critical characteristics which could aid architects in optimizing the design. Second, there is an increasing variability both in the process parameters and in environmental variables such as power supply and temperature. These increasing variations are directly reflected in microprocessor yield statistics as more manufactured chips fail to meet performance targets. Furthermore, it will be difficult if not impossible to recover from these losses with architectural modifications, which do not directly consider the circuit level causes. Without intervention, the design cycle of future processors will be dominated by exhaustive verification related to model complexity and parameter variation. This project offers a paradigm shift where the design cycle features focused analysis of possible failures and the addition of self-monitoring, self-adjusting mechanisms that can both improve the yield, increase the performance, and reduce the requirements of verification. At the heart of this approach lies the design of flexible architectures that can tolerate variations. Particularly, this project involves generation of: (1) variation-aware architectural models which are based on physical properties and are essential for an initial estimate of the critical segments in the processor and possible failures, as well as tradeoff studies, (2) innovative self-adjusting architectures which consider physical aspects of circuits and can be reconfigured based on in-field readings, (3) algorithms for placement of sensing and monitoring elements on the chip as well as the deployment of the adaptive structures and determination of the adaptation type needed, and (4) circuit synthesis algorithms, which determine how to adjust processors for improved yield and performance. This project directly attacks a critical problem in the microprocessor industry: process variation, and hence would have significant commercial and social benefits. Academic benefits include the close interaction between the design automation, circuits, and architecture researchers and educators. This will open new avenues for learning and present a new set of interesting challenges.

当代建筑创新不会减轻纳米级集成电路的最新趋势，并将在未来的微处理器设计中引入重要的瓶颈。首先，高性能电路模型的日益增长的复杂性使得难以确定可以帮助建筑师优化设计的关键特征。其次，过程参数和环境变量（例如电源和温度）的变异性都在增加。这些增加的变化直接反映在微处理器的收益率统计中，因为较生产的芯片无法满足性能目标。此外，如果不能直接考虑电路级别的原因，从这些损失中恢复了这些损失，也将很难恢复。没有干预，将来处理器的设计周期将由与模型复杂性和参数变化有关的详尽验证主导。该项目提供了一个范式转移，设计周期具有针对可能失败的重点分析以及增加自我监控的，自我调整的机制，这些机制既可以提高产量，提高性能并减少验证要求。这种方法的核心在于可以忍受变化的灵活体系结构的设计。 Particularly, this project involves generation of: (1) variation-aware architectural models which are based on physical properties and are essential for an initial estimate of the critical segments in the processor and possible failures, as well as tradeoff studies, (2) innovative self-adjusting architectures which consider physical aspects of circuits and can be reconfigured based on in-field readings, (3) algorithms for placement of sensing and monitoring elements on the芯片以及自适应结构的部署以及所需的适应类型的确定，以及（4）电路合成算法，这些算法决定了如何调整处理器以提高产量和性能。该项目直接攻击微处理器行业的一个关键问题：过程差异，因此将具有重大的商业和社会利益。学术上的好处包括设计自动化，电路和建筑研究人员和教育工作者之间的密切相互作用。这将为学习开辟新的途径，并提出一系列有趣的挑战。