Background Calibration Technique for High-Resolution Analog to Digital Converters in Submicron CMOS

亚微米 CMOS 高分辨率模数转换器的背景校准技术

• 批准号: 0523996
• 负责人: John McNeill
• 金额: --
• 依托单位: Worcester Polytechnic Institute
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2005
• 资助国家: 美国
• 起止时间: 2005-09-01 至 2008-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0523996&HistoricalAwards=false
• 关键词: Background; Calibration; Technique; Resolution; Analog

McNeill 0523996This integrative systems proposal focuses on development of a new class of self-calibrating analog-to-digital converters (ADCs). The new "Split ADC" architecture enables integration of high resolution; self-calibrating ADCs at low cost with advanced digital CMOS integrated circuits (ICs). This capability fills a critical need in a wide range of emerging mixed signal application areas, including integrated sensors for biomedical and homeland security applications. In terms of intellectual merit, the new "Split ADC" architecture represents a genuine creative design breakthrough in response to the specific constraints of advanced digital CMOS processing technology. The PIs previous work in developing the "split ADC" architecture has been proven by successful fabrication and test of a 16bit, 1MSample/s, cyclic ADC. This is an indication of both the validity of the concept to be extended and the PI's ability to successfully complete the proposed work.Broader impacts: The successful completion of the work described in this proposal will extend development of this new class of self-calibrating ADCs to the important application area of interleaved ADCs. The project will also contribute to the goal of expanding education by supporting a Ph.D. student to perform the bulk of the research work. Results of this research will be used as a module in a graduate-level circuit design course. Additionally, the PI will involve undergraduate students in this research effort.

McNeill 0523996这一集成系统建议着重于开发新的一类自校准类似物到数字转换器（ADC）。新的“拆分ADC”体系结构可以集成高分辨率；高级数字CMOS集成电路（ICS）以低成本的自我校准ADC。该能力满足了各种新兴的混合信号应用领域的关键需求，包括用于生物医学和国土安全应用的集成传感器。在智力优点方面，新的“拆分ADC”体系结构代表了对高级数字CMOS处理技术的特定约束的真正创意设计的突破。 PIS先前在开发“拆分ADC”体系结构的工作已通过成功制造和测试16位，1mmplame/s，Cyclic ADC证明。这表明要扩展该概念的有效性以及PI成功完成所提出的工作的能力。Broader的影响：该提案中描述的工作的成功完成将扩展到这一新的自我校准ADC的开发到交织ADC的重要应用领域。 该项目还将通过支持博士学位来扩大教育的目标有助于扩大教育。学生进行大部分研究工作。 这项研究的结果将用作研究生级电路设计课程中的模块。此外，PI将涉及本科生参加这项研究工作。