Integrated Framework for Reliability- and Process-Variation Aware Design Methodology for VLSI Circuits

VLSI 电路可靠性和工艺变化感知设计方法的集成框架

• 批准号: 0429930
• 负责人: Muhammad Alam
• 金额: $ 15万
• 依托单位: Purdue University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2004
• 资助国家: 美国
• 起止时间: 2004-09-01 至 2007-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0429930&HistoricalAwards=false
• 关键词: Integrated; Framework; Reliability; Process; Variation

PROPOSAL NO: 0429930INSTITUTION: Purdue UniversityPRINCIPAL INVESTIGATOR: Alam, Muhammad and Roy, KaushikTITLE: Integrated Framework for Reliability- and Process-Variation Aware Design Methodology for VLSI CircuitsAbstractModern integrated circuits (IC) contain tens of millions of transistors. Traditional design of these integrated circuits has relied on the fact that these transistors have almost identical characteristics when they are initially made, and that the characteristics change little during their subsequent usage. Therefore, IC designers have worried about other things like the size of the IC, its speed, battery life, ease of debugging for errors, etc. And this traditional design approach has worked fine for last 25 years. But now-a-days the transistors are becoming so tiny that it is getting impossible to ensure that they have same geometrical and physical characteristics. Equally important, the characteristics of the small transistors can change rapidly when the consumer uses the product. ThePIs hope to answer the question as to how one can design an integrated circuit if one can no longer rely on the uniformity of the transistors, but must account for the fact that each transistor is slightly different and that its property changes with time. One can always assume the very worst case and design for the slowest transistor, but clearly that would be very wasteful. The project are proposes that a much better approach would be to first accurately understand why and how the transistor parameter change (of fluctuate) and to account for this variation explicitly from the very beginning of the IC design process. The design technique is no longer deterministic as it once were, but it now involves statistical design methodologies like making the slower transistors a little wider (transistor sizing) to compensate for their lack of speed or making sure that the architecture distributes the usage burden among a number of transistors so no one transistor becomes so slow that the IC fails. This new approach may allow one to make faster or less power-consuming ICs with a given set of transistors, because designers can now be more aggressive in their design. This in turn, may also allow more time to find alternatives to CMOS, and ease the eventual transition to post-CMOS devices and systems.

提案编号：0429930 Institution：Purdue University Principal研究者：Alam，Muhammad和Roy，Kaushiktitle：可靠性和过程变化的集成框架 - VLSI CircuitsAbsTractrestract Modertant Modegern Moderated Coussitits（IC）包含数百万跨跨跨跨跨跨跨跨跨跨跨跨跨跨跨跨跨的跨性别的框架。这些综合电路的传统设计依赖于以下事实：这些晶体管最初制造时具有几乎相同的特征，并且在随后的使用过程中这些特性变化不大。因此，IC设计师担心其他事情，例如IC的大小，其速度，电池寿命，易于调试的错误等等，并且这种传统的设计方法在过去的25年中运行良好。但是现在，晶体管变得如此微小，以至于不可能确保它们具有相同的几何特征和物理特征。同样重要的是，当消费者使用该产品时，小晶体管的特性可能会迅速变化。 Thepis希望回答一个问题，即如果人们不再依靠晶体管的统一性，可以设计一个集成电路，但必须考虑到每个晶体管略有不同并且其属性随时间而变化的事实。人们总是可以假设最慢的晶体管的最坏情况和设计，但显然这将非常浪费。该项目提出，一种更好的方法是首先准确了解晶体管参数（波动）的变化以及如何从IC设计过程的开始，并明确考虑这种变化。该设计技术不再像以前那样确定性，但现在涉及统计设计方法，例如使较慢的晶体管更宽（晶体管尺寸），以弥补其缺乏速度或确保建筑在建筑中分配使用负担晶体管的数量，因此没有一个晶体管变得如此慢，以至于IC失败了。这种新方法可能会使人们使用一组给定的晶体管制作更快或更少的功率耗尽IC，因为设计师现在可以更具侵略性。反过来，这也可能会给更多时间找到CMO的替代方案，并最终过渡到CMOS后设备和系统。