NIRT: Spatially Ordered Self-Assembled Quantum Dot Gate Low Voltage/Power, High Speed Nanoscale Flash Memories

NIRT：空间有序自组装量子点门低电压/功耗高速纳米级闪存

• 批准号: 0304026
• 负责人: Sanjay Banerjee
• 金额: --
• 依托单位: University of Texas at Austin
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2003
• 资助国家: 美国
• 起止时间: 2003-09-15 至 2008-02-29
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0304026&HistoricalAwards=false
• 关键词: NIRT; Spatially; Ordered; Self; Assembled

This NIRT proposal focuses on the technology and underlying science for high-speed, low power, high-density Si-Ge-C planar and vertical Flash Electrically Erasable and Programmable Read Only Memories (EEPROMs) using high-k dielectrics and Si-Ge-C or metal Self Assembled Quantum Dot (SAQD) floating gates. Conventional flash EEPROMs have several serious drawbacks and this research investigates new memory cell structures with the goal of providing a compact, low-power, high-speed (programming, erase and read operation) semiconductor memory technology for future integrated circuit devices. The research will experimentally and theoretically explore: (1) the growth of ordered arrays of Si-Ge-C and metal nanoparticles on dielectric surfaces, employing chemical/physical vapor deposition (CVD or PVD) techniques that uncouple nucleation from growth. We will try to achieve high densities, spatial control and narrow particle size distributions, in concert with imprint lithography techniques; (2) development of high-k-based flash memory to allow for physically thicker, but electrically thinner "equivalent" oxides; (3) low band gap, high mobility Si-Ge-C heterolayers in the channel of planar flash cells to act as "cold cathodes"; (4) vertical nanoscale flash EEPROMs, which will allow bandgap engineering using Si-Ge-C along the channel; 5) first-principles modeling of nanoparticle structure evolution, including nucleation, growth, crystallization, and encapsulation within the dielectric to support experimental growth studies; and 6) theoretical modeling of hot carrier transport by hydrodynamic and Monte Carlo simulation, tunneling transport using transfer matrix methods, and quantum transport calculations of Coulomb blockade effects in the SAQDs. SAQDs enhance charge retention and VT stability, as well as possibly allow multi-level storage based on Coulomb blockade. High-k-based dielectrics should provide high capacitive coupling, without sacrificing non-volatility, and allow for lower-voltage and/or higher-speed operation through the potential-reduction in barrier height to channel hot electron (CHE) injection and tunneling, and increased device lifetime because of the thicker tunneling barriers under low field storage conditions. Si-Ge-C planar flash cells should enhance impact ionization and CHE, for reduction of operating voltages/powers and increasing programming speed. Vertical cell structures will allow the highest possible densities in a so-called cross-point architecture where the cell is located at the intersection of the wordline and bitline. The collaborative nature of the research will enhance the graduate student experience and develop team-building skills. The four graduate students will benefit from the joint supervision of the four co-PIs. Through this experience they will learn more about the areas outside their major area of study, and gain an appreciation of how other disciplines define problems and approach their solution. They will also get a chance to mentor under-grad students and get them excited with cutting-edge nanotechnology research. To bring the excitement of nanoscale objects and devices to the general public and to pre-college students, the co-investigators and their students will develop, produce and display exhibits that explain these revolutionary devices and their fabrication. The exhibits will be: used at local and regional science fun days and fairs; made available for display at regional K-12 schools and museums; and used in a traveling exhibit trailer that brings engineering awareness to underrepresented constituencies in Texas. We will have a strong industrial linkage with Dr. Bruce White, Manager of "Advanced Materials and Memories" at Motorola, Austin.

该 NIRT 提案重点关注使用高 k 电介质和 Si-Ge-C 的高速、低功耗、高密度 Si-Ge-C 平面和垂直闪存电可擦除可编程只读存储器 (EEPROM) 的技术和基础科学。 C 或金属自组装量子点 (SAQD) 浮栅。传统的闪存 EEPROM 有几个严重的缺点，本研究研究了新的存储单元结构，旨在为未来的集成电路器件提供紧凑、低功耗、高速（编程、擦除和读取操作）半导体存储技术。该研究将通过实验和理论探索：(1) 采用化学/物理气相沉积（CVD 或 PVD）技术，将成核与生长分离，在电介质表面上生长有序的 Si-Ge-C 和金属纳米颗粒阵列。 我们将尝试与压印光刻技术相结合，实现高密度、空间控制和窄粒度分布； (2) 开发基于高 k 的闪存，以实现物理上更厚但电学上更薄的“等效”氧化物； (3)平面闪存电池沟道中的低带隙、高迁移率Si-Ge-C异质层充当“冷阴极”； (4) 垂直纳米级闪存 EEPROM，允许沿沟道使用 Si-Ge-C 进行带隙工程； 5) 纳米颗粒结构演化的第一原理建模，包括成核、生长、结晶和电介质内的封装，以支持实验生长研究； 6）通过流体动力学和蒙特卡罗模拟进行热载流子传输的理论建模，使用传输矩阵方法进行隧道传输，以及SAQD中库仑阻塞效应的量子传输计算。 SAQD 增强了电荷保持和 VT 稳定性，并可能允许基于库仑封锁的多级存储。 高 k 基电介质应提供高电容耦合，而不牺牲非易失性，并通过势垒高度的电位降低来实现较低电压和/或较高速度操作，以通道热电子 (CHE) 注入和隧道效应，由于在低场存储条件下隧道势垒更厚，因此器件寿命更长。 Si-Ge-C 平面闪存单元应增强碰撞电离和 CHE，以降低工作电压/功率并提高编程速度。 垂直单元结构将允许所谓的交叉点架构中的最高可能密度，其中单元位于字线和位线的交叉点处。研究的协作性质将增强研究生的体验并培养团队建设技能。 这四名研究生将受益于四名联合 PI 的联合监督。 通过这种经验，他们将更多地了解其主要研究领域之外的领域，并了解其他学科如何定义问题和解决问题的方法。他们还将有机会指导本科生并让他们对尖端纳米技术研究感到兴奋。为了让普通公众和大学预科学生对纳米级物体和设备感到兴奋，联合研究人员和他们的学生将开发、制作和展示展品，解释这些革命性的设备及其制造过程。 展品将： 用于当地和地区的科学欢乐日和博览会；可在地区 K-12 学校和博物馆展示；并用于流动展览拖车，为德克萨斯州代表性不足的选区带来工程意识。我们将与奥斯汀摩托罗拉公司“先进材料和存储器”经理 Bruce White 博士建立牢固的产业联系。