CISE Postdoctoral Program: Research in Computer Aided Design of VLSI Circuits with Emphasis on Deep Submicron Technology

CISE博士后项目：以深亚微米技术为重点的VLSI电路计算机辅助设计研究

• 批准号: 9625910
• 负责人: Ernest Kuh
• 金额: $ 2.09万
• 依托单位: University of California-Berkeley
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1996
• 资助国家: 美国
• 起止时间: 1996-03-15 至 1998-02-28
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9625910&HistoricalAwards=false
• 关键词: CISE; Postdoctoral; Program; Research; Computer

9625910 Kuh, Ernest S. University of California, Berkeley CISE Postdoctoral Program: Research in Computer Aided Design of VLSI Circuits with Emphasis on Deep Submicron Technology This award supports associate John P. Lillis. With the advent of deep submicron technology, the VLSI community is now faced with many new technical challenges which are currently inadequately addressed by the state of the art in Computer Aided Design for VLSI circuits. Because of the scaling of feature size in the submicron domain, performance of VLSI systems is now largely dominated by interconnect delay. Some powerful techniques for addressing this interconnect dominance are timing optimization by buffer insertion, wire sizing and performance driven routing. We propose that the time during the award period be used to further develop these techniques into a mature, cohesive set of tools. Among the research objectives of the proposals are (1) development of algorithms for routing and buffer insertion to address the problems of electromigration and crosstalk noise, (2) experimental evaluation of gate replication techniques for timing optimization and (3) integration of the optimization techniques at a higher level in the physical layout process which included circuit placement. All of these topics are of great practical importance in deep submicron systems of today and the future.

9625910 KUH，ERNEST S.加利福尼亚大学，伯克利大学CISE博士后计划：计算机辅助设计VLSI电路的研究，重点是深subsicron Technology，该奖项支持同事John P. Lillis。 随着深度统一技术的出现，VLSI社区现在面临着许多新的技术挑战，目前，这些技术在计算机辅助设计中针对VLSI Circuits的最新技术无法充分解决。 由于亚微米域中特征大小的缩放，VLSI系统的性能现在主要由互连延迟主导。 解决这种互连优势的一些强大技术是通过缓冲插入，电线尺寸和性能驱动的路由来优化时序。 我们建议将奖励期间的时间用于将这些技术进一步开发成一组成熟的，具有凝聚力的工具。 提案的研究目标包括（1）开发用于解决电气移动和串扰噪声问题的路由和缓冲插入算法，（2）实验性评估，用于定时优化的栅极复制技术以及（3）（3）在物理布局过程中优化技术集成在物理布局过程中，包括电路安装在内。 所有这些主题在当今和未来的深层次要系统中至关重要。