RIA: Fault Tolerance in Analog VLSI Focal Plane Processors

RIA：模拟 VLSI 焦平面处理器的容错

• 批准号: 9010364
• 负责人: Andreas Andreou
• 金额: $ 7.63万
• 依托单位: Johns Hopkins University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1990
• 资助国家: 美国
• 起止时间: 1990-07-01 至 1993-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9010364&HistoricalAwards=false
• 关键词: RIA; Fault; Tolerance; Analog; VLSI

Andreou Analog VLSI is a promising approach to the design of systems for machine vision since it leads to distributed, data driven architectures, that map the light stimuli directly to the crux of computing hardware, the silicon substrate. This emerging class of signal processing systems is based on relatively simple computational primitives such as logarithmic photodetectors, aggregating resistive networks and coupled non-linear resistive networks. Furthermore, there are power and area efficient features that make them attractive for wafer scale integration. However, manufacturing of such systems at the wafer scale will strongly depend on establishing design methodologies that make them robust to defects in the fabrication process. Equally important, these must be augmented with yield estimation models as well as testing and failure analysis procedures. The above issues are addressed in this research in a comprehensive program that involves both analytical calculations and experimental studies.

Andreou Analog VLSI是机器视觉系统设计系统设计的一种有前途的方法，因为它导致了分布式的数据驱动体系结构，将光刺激直接映射到计算硬件的症状，即硅基板。 这种新兴的信号处理系统类别基于相对简单的计算原始词，例如对数光电探测器，集合电阻网络和耦合的非线性电阻网络。 此外，还有一些功率和区域效率的功能，使其对晶圆量表集成具有吸引力。 但是，在晶圆量表上制造此类系统将在很大程度上取决于建立设计方法，使它们在制造过程中的缺陷使它们有力。 同样重要的是，必须通过产量估计模型以及测试和故障分析程序来增强这些内容。 在本研究中，在涉及分析计算和实验研究的综合计划中解决了上述问题。