An analog VLSI chip with asynchronous interface for auditory feature extraction

We describe the architecture and circuit implementation of an analog VLSI feature extraction chip that has an asynchronous digital interface and is designed to serve as an auditory based front-end for a digit recognition system. The single chip system encodes signal energies and zero crossing time intervals of frequency components in a cochlear filter bank. The chip has been fabricated in a 1.2 /spl mu/m n-well, double polysilicon, double metal CMOS process and it is fully functional. Power consumption when operated from a 5 V supply is only a few milliwatts.

我们描述了一种模拟超大规模集成电路特征提取芯片的架构和电路实现，该芯片具有异步数字接口，旨在用作数字识别系统的基于听觉的前端。这个单芯片系统对耳蜗滤波器组中频率成分的信号能量和过零时间间隔进行编码。该芯片采用1.2微米n阱、双层多晶硅、双层金属CMOS工艺制造，功能完备。在5伏电源下工作时，功耗仅为几毫瓦。