Read your Circuit: Leveraging Word Embedding to Guide Logic Optimization

To tackle the involved complexity, Electronic Design Automation (EDA) tools are broken in well-defined steps, each operating at different abstraction levels. Higher levels of abstraction shorten the flow run-time while sacrificing correlation with the physical circuit implementation. Bridging this gap between Logic Synthesis tool and Physical Design (PnR) tools is key to improve Quality of Results (QoR), while possibly shorting the time-to-market. To address this problem, in this work, we formalize logic paths as sentences, with the gates being a bag of words. Thus, we show how word embedding can be leveraged to represent generic paths and predict if a given path is likely to be critical post-PnR. We present the effectiveness of our approach, with accuracy over than 90% for our test-cases. Finally, we give a step further and introduce an intelligent and non-intrusive flow that uses this information to guide optimization. Our flow presents up to 15.53% area delay product (ADP) and 18.56% power delay product (PDP), compared to a standard flow.

为了解决所涉及的复杂性，电子设计自动化（EDA）工具以明确的步骤破坏，每个工具都以不同的抽象水平运行。较高的抽象水平缩短了流动时间，同时牺牲了与物理电路实现的相关性。在逻辑合成工具和物理设计（PNR）工具之间桥接这一差距是提高结果质量（QOR）的关键，同时可能会缩短市场时间。为了解决这个问题，在这项工作中，我们将逻辑路径正式为句子，而大门是一袋单词。因此，我们展示了如何利用单词嵌入来表示通用路径，并预测给定路径是否可能是PNR关键的PNR。我们介绍了方法的有效性，对于测试案例，准确性超过90％。最后，我们更进一步，引入了一种智能且非侵入性的流，该流程使用此信息来指导优化。与标准流相比，我们的流量呈现高达15.53％的面积延迟产品（ADP）和18.56％的功率延迟产品（PDP）。