Two-stage Pipelined SRAM Design Based on 14nm FinFET Process

In this paper, we propose a two-stage pipeline architecture for Static Random Memories (SRAM), which can reduce the decoder delay and thus effectively improve the memory operation speed. The proposed two-stage pipeline architecture divides the SRAM in the conventional architecture into two parts, the decoder and the read/write path, by a hierarchical approach and uses registers to connect these two parts. Simulation results using SMIC 14nm FinFET devices show that for a high-speed SRAM of 512words*16bits, the access speed of the array is improved by 21% compared to the SRAM under the conventional architecture. This design not only implements the read/write function of the two-stage pipelined SRAM, but also provides some optimization of its performance.

在本文中，我们针对静态随机存储器（SRAM）提出了一种两级流水线架构，该架构能够减少译码器延迟，从而有效提高存储器的运行速度。所提出的两级流水线架构通过分层方法将传统架构中的SRAM分为译码器和读/写路径两部分，并使用寄存器连接这两部分。使用中芯国际14nm鳍式场效应晶体管器件的仿真结果表明，对于一个512字×16位的高速SRAM，与传统架构下的SRAM相比，阵列的访问速度提高了21%。这种设计不仅实现了两级流水线SRAM的读/写功能，还对其性能进行了一些优化。