FlowTune: Practical Multi-armed Bandits in Boolean Optimization

Recent years have seen increasing employment of decision intelligence in electronic design automation (EDA), which aims to reduce the manual efforts and boost the design closure process in modern toolflows. However, existing approaches either require a large number of labeled data for training or are limited in practical EDA toolflow integration due to computation overhead. This paper presents a generic end-to-end and high-performance domain-specific, multi-stage multi-armed bandit framework for Boolean logic optimization. This framework addresses optimization problems on a) And-Inv-Graphs (# nodes), b) Conjunction Normal Form (CNF) minimization (# clauses) for Boolean Satisfiability, c) post static timing analysis (STA) delay and area optimization for standard-cell technology mapping, and d) FPGA technology mapping for 6-in LUT architectures. Moreover, the proposed framework has been integrated with ABC [1], Yosys [2], VTR [3], and industrial tools. The experimental results demonstrate that our framework outperforms both hand-crafted flows [1] and ML explored flows [4], [5] in quality of results, and is orders of magnitude faster compared to ML-based approaches [4], [5].

近年来，电子设计自动化（EDA）中决策情报的就业越来越多，该智能旨在减少体力劳动并促进现代工具流中的设计封闭过程。但是，现有方法要么需要大量的标记数据进行培训，要么由于计算开销而受到实用的EDA工具流集成的限制。本文介绍了用于布尔逻辑优化的通用端到端和高性能域特异性，多阶段的多臂匪徒框架。该框架解决了a）和inv-graphs（＃nodes），b）连词正常形式（cnf）最小化（＃条款）的优化问题，以实现布尔值满意度，c）静态时序分析（STA）延迟和标准的面积延迟和面积优化 - 细胞技术映射和D）6英寸LUT体系结构的FPGA技术映射。此外，提议的框架已与ABC [1]，Yosys [2]，VTR [3]和工业工具集成在一起。实验结果表明，我们的框架的表现优于手工制作的流[1]和ML探索的结果[4]，[5]的结果质量，并且与基于ML的方法相比[4]，[5 ]。