In-Memory Computing with Memristor Arrays

Memristors with tunable non-volatile resistance states offer the potential for in-memory computing that mitigates the von-Neumann bottleneck. We build a large scale memristor array by integrating a transistor array with Ta/HfO2 memristors that have stable multilevel resistance states and linear IV characteristic. With off-chip peripheral driving circuits, the memristor chip is capable of high-precision analog computing and online learning. We demonstrate a weight-update scheme that provides linear and symmetric potentiation and depression with no more than two pulses for each cell. We train the array as a single-layer fully-connected feedforward neural network for the WDBC data base and achieve 98% classification accuracy. We further partition the array into a two-layer network, which achieves 91.71% classification accuracy for MNIST database experimentally. The system demonstrates high defect tolerance and excellent speed-energy efficiency.

具有可调非易失性电阻状态的忆阻器为内存计算提供了潜力，缓解了冯·诺依曼瓶颈。我们通过将晶体管阵列与具有稳定多级电阻状态和线性I - V特性的Ta/HfO₂忆阻器集成，构建了一个大规模忆阻器阵列。借助片外外围驱动电路，该忆阻器芯片能够进行高精度模拟计算和在线学习。我们展示了一种权重更新方案，对于每个单元，只需不超过两个脉冲即可实现线性且对称的增强和抑制。我们将该阵列作为一个单层全连接前馈神经网络针对威斯康星州乳腺癌诊断（WDBC）数据库进行训练，实现了98%的分类准确率。我们进一步将该阵列划分为一个两层网络，针对MNIST数据库进行实验时，实现了91.71%的分类准确率。该系统展示出了高容错性和优异的速度 - 能量效率。