Error Detection Architectures for Hardware/Software Co-Design Approaches of Number-Theoretic Transform

Number-theoretic transform (NTT) is an efficient polynomial multiplication technique of lattice-based post-quantum cryptography including Kyber which is standardized as the NIST key encapsulation mechanism (KEM) in 2022. Prominent NTT architectures have recently been implemented on hardware/software coprocessors. In this article, we introduce new error detection schemes embedded efficiently in the NTT accelerator architecture, detecting both transient and permanent faults. By encoding the operands with two approaches, i.e., negating and swapping, we detect the faults in such constructions after recomputing and decoding. Through simulation, our schemes show high error coverage for the stuck-at fault model. Moreover, we implement the schemes on field-programmable gate array (FPGA) and assure that acceptable overhead is achieved for performance and implementation metrics. The low overhead and high efficiency of our schemes make them suitable for various constrained usage models. Additionally, our schemes are also applicable to similar classical and post-quantum sub-blocks to obtain more reliable respective hardware constructions.

数字理论变换（NTT）是一种有效的多项式乘法技术，基于晶格的后量子加密术，包括Kyber，标准化为2022年的NIST钥匙封装机制（KEM）。 。在本文中，我们介绍了有效嵌入在NTT加速器体系结构中的新的错误检测方案，以检测瞬态和永久性故障。通过用两种方法（即负零交换）编码操作数，我们在重新计算和解码后检测到此类构造中的故障。通过仿真，我们的方案显示了卡住故障模型的高误差覆盖率。此外，我们在现场可编程门阵列（FPGA）上实现了这些方案，并确保可以为性能和实现指标实现可接受的开销。我们计划的低顶和高效率使它们适合各种受约束使用模型。此外，我们的方案还适用于类似的经典和量词后亚块，以获得更可靠的各自的硬件结构。