Cache design for mixed criticality real-time systems

Shared caches in mixed criticality systems are a source of interference for safety critical tasks. Shared memory not only leads to worst-case execution time (WCET) pessimism, but also affects the response time of safety critical tasks. In this paper, we present a criticality aware cache design which implements a Least Critical (LC) cache replacement policy, where a least recently used non-critical cache line is replaced during a cache miss. The cache acts as a Least Recently Used (LRU) cache if there are no critical lines or if all cache lines are critical in a set. In our design, data within a certain address space is given higher preference in the cache. These critical address spaces are configured using critical address range (CAR) registers. The new cache design was implemented in a Leon3 processor core, a 32bit processor compliant with the SPARC V8 architecture. Experimental results are presented that illustrate the impact of the Least Critical cache replacement policy on the response time of critical tasks, and on overall application performance as compared to a conventional LRU cache policy.

混合临界系统中的共享缓存是对安全关键任务的干预来源。共享内存不仅会导致最坏的执行时间（WCET）悲观，而且还会影响安全至关重要的任务的响应时间。在本文中，我们提出了一个关键的意识到的缓存设计，该缓存设计实现了至少关键（LC）缓存替换策略，其中至少最近使用的非关键缓存线在缓存失误期间被替换。如果没有临界线或所有缓存线至关重要，则该缓存至少是最近使用的（LRU）缓存。在我们的设计中，在高速缓存中，在某个地址空间内的数据更高。这些关键的地址空间是使用关键地址范围（CAR）寄存器配置的。新的缓存设计是在LEON3处理器Core中实现的，Leon3处理器Core是一个符合SPARC V8体系结构的32位处理器。提出了实验结果，以说明与常规的LRU缓存策略相比，最小关键的缓存替换政策对关键任务响应时间以及对整体应用程序性能的影响。